From 24dbb7ab939f40ba530634b4db94bf0bf55ab185 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Tiago=20M=C3=BCck?= Date: Fri, 26 Jul 2019 15:06:26 -0500 Subject: [PATCH] cpu-o3: fix store-release issuing MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Requests from stores with release semantics are only issued when they are at the head of the store queue. Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27134 Reviewed-by: Anthony Gutierrez Maintainer: Anthony Gutierrez Tested-by: kokoro Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com> --- src/cpu/o3/lsq_unit_impl.hh | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index f7fb3fe36..7383c6f9f 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1,6 +1,6 @@ /* - * Copyright (c) 2010-2014, 2017-2019 ARM Limited + * Copyright (c) 2010-2014, 2017-2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -753,6 +753,21 @@ LSQUnit::writebackStores() DynInstPtr inst = storeWBIt->instruction(); LSQRequest* req = storeWBIt->request(); + + // Process store conditionals or store release after all previous + // stores are completed + if ((req->mainRequest()->isLLSC() || + req->mainRequest()->isRelease()) && + (storeWBIt.idx() != storeQueue.head())) { + DPRINTF(LSQUnit, "Store idx:%i PC:%s to Addr:%#x " + "[sn:%lli] is %s%s and not head of the queue\n", + storeWBIt.idx(), inst->pcState(), + req->request()->getPaddr(), inst->seqNum, + req->mainRequest()->isLLSC() ? "SC" : "", + req->mainRequest()->isRelease() ? "/Release" : ""); + break; + } + storeWBIt->committed() = true; assert(!inst->memData); -- 2.30.2