From 24e6fba50010d9d1efce0d9d3cbcf61dc3aebf0e Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 3 May 2017 17:24:43 -0700 Subject: [PATCH] i965/vs: Set uses_vertexid and friends from brw_compile_vs MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Alejandro Piñeiro Reviewed-by: Kenneth Graunke --- src/intel/compiler/brw_fs_visitor.cpp | 6 ------ src/intel/compiler/brw_vec4.cpp | 17 +++++++++++++++++ src/intel/compiler/brw_vec4_vs_visitor.cpp | 5 ----- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index cd411481d84..dd09fbdd64c 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -38,26 +38,21 @@ fs_visitor::emit_vs_system_value(int location) fs_reg *reg = new(this->mem_ctx) fs_reg(ATTR, 4 * _mesa_bitcount_64(nir->info.inputs_read), BRW_REGISTER_TYPE_D); - struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(prog_data); switch (location) { case SYSTEM_VALUE_BASE_VERTEX: reg->offset = 0; - vs_prog_data->uses_basevertex = true; break; case SYSTEM_VALUE_BASE_INSTANCE: reg->offset = REG_SIZE; - vs_prog_data->uses_baseinstance = true; break; case SYSTEM_VALUE_VERTEX_ID: unreachable("should have been lowered"); case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE: reg->offset = 2 * REG_SIZE; - vs_prog_data->uses_vertexid = true; break; case SYSTEM_VALUE_INSTANCE_ID: reg->offset = 3 * REG_SIZE; - vs_prog_data->uses_instanceid = true; break; case SYSTEM_VALUE_DRAW_ID: if (nir->info.system_values_read & @@ -67,7 +62,6 @@ fs_visitor::emit_vs_system_value(int location) BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID))) reg->nr += 4; reg->offset = 0; - vs_prog_data->uses_drawid = true; break; default: unreachable("not reached"); diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 9f280840091..9366b893068 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2797,9 +2797,26 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data, nr_attribute_slots++; } + if (shader->info.system_values_read & + BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX)) + prog_data->uses_basevertex = true; + + if (shader->info.system_values_read & + BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE)) + prog_data->uses_baseinstance = true; + + if (shader->info.system_values_read & + BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE)) + prog_data->uses_vertexid = true; + + if (shader->info.system_values_read & + BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID)) + prog_data->uses_instanceid = true; + /* gl_DrawID has its very own vec4 */ if (shader->info.system_values_read & BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID)) { + prog_data->uses_drawid = true; nr_attribute_slots++; } diff --git a/src/intel/compiler/brw_vec4_vs_visitor.cpp b/src/intel/compiler/brw_vec4_vs_visitor.cpp index 0cec77990d6..2a19788c954 100644 --- a/src/intel/compiler/brw_vec4_vs_visitor.cpp +++ b/src/intel/compiler/brw_vec4_vs_visitor.cpp @@ -45,25 +45,20 @@ vec4_vs_visitor::make_reg_for_system_value(int location) switch (location) { case SYSTEM_VALUE_BASE_VERTEX: reg->writemask = WRITEMASK_X; - vs_prog_data->uses_basevertex = true; break; case SYSTEM_VALUE_BASE_INSTANCE: reg->writemask = WRITEMASK_Y; - vs_prog_data->uses_baseinstance = true; break; case SYSTEM_VALUE_VERTEX_ID: case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE: reg->writemask = WRITEMASK_Z; - vs_prog_data->uses_vertexid = true; break; case SYSTEM_VALUE_INSTANCE_ID: reg->writemask = WRITEMASK_W; - vs_prog_data->uses_instanceid = true; break; case SYSTEM_VALUE_DRAW_ID: reg = new(mem_ctx) dst_reg(ATTR, VERT_ATTRIB_MAX + 1); reg->writemask = WRITEMASK_X; - vs_prog_data->uses_drawid = true; break; default: unreachable("not reached"); -- 2.30.2