From 250659f9466838c67bedd771fe32984cd64ffa57 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 Mar 2023 17:19:41 +0000 Subject: [PATCH] update pseudocode for dsld/dsrd to note that only when Rc=1 is setting overflow=1 relevant. for ls003 --- openpower/isa/svfixedarith.mdwn | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn index 1b6efd49..6ce79fb6 100644 --- a/openpower/isa/svfixedarith.mdwn +++ b/openpower/isa/svfixedarith.mdwn @@ -70,7 +70,7 @@ Pseudo-code: Special Registers Altered: - None + XER.OV # [DRAFT] Double-width Shift Left Doubleword @@ -86,9 +86,9 @@ Pseudo-code: mask <- MASK(0, 63-n) RT <- (v[0:63] & mask) | ((RC) & ¬mask) RS <- v[0:63] & ¬mask - overflow <- 0 + overflow <- 0 # relevant only when Rc=1 if RS != [0]*64 then - overflow <- 1 + overflow <- 1 # relevant only when Rc=1 Special Registers Altered: @@ -108,9 +108,9 @@ Pseudo-code: mask <- MASK(n, 63) RT <- (v[0:63] & mask) | ((RC) & ¬mask) RS <- v[0:63] & ¬mask - overflow <- 0 + overflow <- 0 # relevant only when Rc=1 if RS != [0]*64 then - overflow <- 1 + overflow <- 1 # relevant only when Rc=1 Special Registers Altered: -- 2.30.2