From 25180f8aefdfb363742aa577363184fd2a43c0b6 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Mon, 4 Feb 2002 16:27:22 +0000 Subject: [PATCH] If a v5 architecture is detected, assume it might be an XScale binary, since there is no way to distinguish between the two in the COFF file format. --- sim/arm/ChangeLog | 6 ++++++ sim/arm/wrapper.c | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index 3b954d09bba..fbfc595a405 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,9 @@ +2002-02-04 Nick Clifton + + * wrapper.c: If a v5 architecture is detected, assume it might be + an XScale binary, since there is no way to distinguish between + the two in the COFF file format. + 2002-01-10 Nick Clifton * arminit.c (ARMul_Abort): Fix parameters passed to CPRead[13]. diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c index 524377d374c..c2fd8bececd 100644 --- a/sim/arm/wrapper.c +++ b/sim/arm/wrapper.c @@ -234,6 +234,15 @@ sim_create_inferior (sd, abfd, argv, env) break; case bfd_mach_arm_5: + /* This is a special case in order to support COFF based ARM toolchains. + The COFF header does not have enough room to store all the different + kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default + to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5 + machine type here, we assume it could be any of the above architectures + and so select the most feature-full. */ + ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop); + break; + case bfd_mach_arm_5T: ARMul_SelectProcessor (state, ARM_v5_Prop); break; -- 2.30.2