From 251cff8f71520e2c9458000af34460a2d3014d3e Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 7 May 2022 13:25:55 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 4b392ee00..5aa83bdde 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -587,8 +587,9 @@ cache-coherent Memory-access Protocol that is integrated into IBM's Supercomputi has OpenCAPI Memory interfaces, and requires an OMI-to-DDR4/5 Bridge PHY to connect to standard DIMMs. -Extra-V appears to be a remarkable research project that, by leveraging -OpenCAPI, assuming that the map of edges in any given arbitrary data graph +Extra-V appears to be a remarkable research project based on OpenCAPI that, +by assuming that the map of edges (excluding the actual data) +in any given arbitrary data graph could be kept by the main CPU in-memory, could distribute and delegate a limited-capability deterministic but most importantly *data-dependent* node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier). A miniature processor -- 2.30.2