From 252ae33b0d21fcda1ba11ffc99e805f80889b0b2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 13 Feb 2021 18:29:06 +0000 Subject: [PATCH] update svp64 unit test comments --- src/soc/decoder/isa/test_caller_svp64.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py index c5b9d92c..89c6068e 100644 --- a/src/soc/decoder/isa/test_caller_svp64.py +++ b/src/soc/decoder/isa/test_caller_svp64.py @@ -26,14 +26,16 @@ class DecoderTestCase(FHDLTestCase): # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v' ]) - lst = list(isa) print ("listing", lst) + + # initial values in GPR regfile initial_regs = [0] * 32 initial_regs[9] = 0x1234 initial_regs[10] = 0x1111 initial_regs[5] = 0x4321 initial_regs[6] = 0x2223 + # SVSTATE (in this case, VL=2) svstate = SVP64State() svstate.vl[0:7] = 2 # VL svstate.maxvl[0:7] = 2 # MAXVL @@ -53,14 +55,16 @@ class DecoderTestCase(FHDLTestCase): # r1 is scalar so ENDS EARLY isa = SVP64Asm(['sv.add 1, 5.v, 9.v' ]) - lst = list(isa) print ("listing", lst) + + # initial values in GPR regfile initial_regs = [0] * 32 initial_regs[9] = 0x1234 initial_regs[10] = 0x1111 initial_regs[5] = 0x4321 initial_regs[6] = 0x2223 + # SVSTATE (in this case, VL=2) svstate = SVP64State() svstate.vl[0:7] = 2 # VL svstate.maxvl[0:7] = 2 # MAXVL @@ -79,14 +83,16 @@ class DecoderTestCase(FHDLTestCase): # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 isa = SVP64Asm(['sv.add 1.v, 5, 9.v' ]) - lst = list(isa) print ("listing", lst) + + # initial values in GPR regfile initial_regs = [0] * 32 initial_regs[9] = 0x1234 initial_regs[10] = 0x1111 initial_regs[5] = 0x4321 initial_regs[6] = 0x2223 + # SVSTATE (in this case, VL=2) svstate = SVP64State() svstate.vl[0:7] = 2 # VL svstate.maxvl[0:7] = 2 # MAXVL -- 2.30.2