From 255f26cf45361091244631d2c61d7f739f6146da Mon Sep 17 00:00:00 2001 From: Slan Date: Fri, 22 Jan 2021 11:53:02 +0200 Subject: [PATCH] Fix broken timing constraints --- nmigen/vendor/xilinx_7series.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py index 25bfa28..128035d 100644 --- a/nmigen/vendor/xilinx_7series.py +++ b/nmigen/vendor/xilinx_7series.py @@ -421,12 +421,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform): m.d.async_ff += o.eq(i) if async_ff_sync._edge == "pos": - m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i) + m.d.comb += ResetSignal("async_ff").eq(async_ff_sync.i) else: - m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i) + m.d.comb += ResetSignal("async_ff").eq(~async_ff_sync.i) m.d.comb += [ - ClockSignal("async_ff").eq(ClockSignal(asnyc_ff_sync._domain)), + ClockSignal("async_ff").eq(ClockSignal(async_ff_sync._domain)), async_ff_sync.o.eq(flops[-1]) ] -- 2.30.2