From 2565a10fa87f402b2bb433d641228d8f9067d444 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 12 Jun 2020 15:03:10 +0100 Subject: [PATCH] debug printout of sim and hardware memory, shows mismatch of depths --- src/soc/fu/compunits/test/test_compunit.py | 23 ++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index 5128ca52..1265ba94 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -152,13 +152,11 @@ class TestRunner(FHDLTestCase): # initialise memory if self.funit == Function.LDST: mem = l0.mem.mem - memlist = [] for i in range(mem.depth//2): data = sim.mem.ld(i*16, 8) data1 = sim.mem.ld(i*16+8, 8) yield mem._array[i].eq(data | (data1<<32)) - print (mem, mem.depth, mem.width) - print ("mem init", list(map(hex,memlist))) + print ("init mem", mem.depth, mem.width, mem) index = sim.pc.CIA.value//4 while index < len(instructions): @@ -237,7 +235,24 @@ class TestRunner(FHDLTestCase): # sigh. hard-coded. test memory if self.funit == Function.LDST: - print ("mem dump", sim.mem.mem) + mem = l0.mem.mem + print ("sim mem dump") + for k, v in sim.mem.mem.items(): + print (" %6x %016x" % (k, v)) + print ("nmigen mem dump") + for i in range(mem.depth//2): + actual_mem = yield mem._array[i] + print (" %6i %032x" % (i*2, actual_mem)) + + for i in range(mem.depth//2): + data = sim.mem.ld(i*16, 8) + data1 = sim.mem.ld(i*16+8, 8) + expected_mem = (data | (data1<<32)) + actual_mem = yield mem._array[i] + self.assertEqual(expected_mem, actual_mem, + "%s %d %x %x" % (code, i, + expected_mem, actual_mem)) + sim.add_sync_process(process) -- 2.30.2