From 25695ba3f27d42fc1e03a60a89c0c0168f0f72d4 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 3 Jul 2020 14:50:43 +0200 Subject: [PATCH] Add DFI injector test case --- gram/test/test_dfii.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py index a14bb20..0cf727e 100644 --- a/gram/test/test_dfii.py +++ b/gram/test/test_dfii.py @@ -114,3 +114,28 @@ class PhaseInjectorTestCase(FHDLTestCase): self.assertEqual((yield pc.cnt), 2) runSimulation(m, process, "test_phaseinjector.vcd") + +class DFIInjectorTestCase(FHDLTestCase): + def generate_dfiinjector(self): + csrhost = CSRHost() + dut = DFIInjector(csrhost.bank, 14, 3, 1, 16, nphases=1) + csrhost.init_bridge() + m = Module() + m.submodules += csrhost + m.submodules += dut + + return (m, dut, csrhost) + + def test_cke(self): + m, dut, csrhost = self.generate_dfiinjector() + + def process(): + yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, (1 << 1), sel=0xF) + yield + self.assertTrue((yield dut.master.phases[0].cke[0])) + + yield from wb_write(csrhost.bus, DFII_CONTROL_ADDR >> 2, 0, sel=0xF) + yield + self.assertFalse((yield dut.master.phases[0].cke[0])) + + runSimulation(m, process, "test_dfiinjector.vcd") -- 2.30.2