From 25844b5683ab0d9a8ba5f4ee01bb5a601a1c8d24 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 21 Dec 2014 11:13:25 +0100 Subject: [PATCH] Fixed "abc" pass for clk and enable signals driven by logic --- passes/abc/abc.cc | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index b1a96dda4..d38e538e3 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -147,6 +147,8 @@ void extract_cell(RTLIL::Cell *cell, bool keepff) return; if (clk_sig != assign_map(cell->getPort("\\C"))) return; + if (GetSize(en_sig) != 0) + return; goto matching_dff; } @@ -692,12 +694,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin } } - if (clk_sig.size() != 0) - mark_port(clk_sig); - - if (en_sig.size() != 0) - mark_port(en_sig); - std::vector cells; cells.reserve(module->cells_.size()); for (auto &it : module->cells_) @@ -714,6 +710,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin for (auto &cell_it : module->cells_) for (auto &port_it : cell_it.second->connections()) mark_port(port_it.second); + + if (clk_sig.size() != 0) + mark_port(clk_sig); + + if (en_sig.size() != 0) + mark_port(en_sig); handle_loops(); -- 2.30.2