From 258b33ecb3853122ea29ec4c66936f19f5943138 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 17 Feb 2019 06:42:21 +0000 Subject: [PATCH] convert to more general base classes, start support for FP64 --- src/add/fmul.py | 4 ++-- src/add/fpbase.py | 22 ++++++++++++++-------- src/add/nmigen_add_experiment.py | 2 +- src/add/nmigen_div_experiment.py | 6 +++--- 4 files changed, 20 insertions(+), 14 deletions(-) diff --git a/src/add/fmul.py b/src/add/fmul.py index 3b605671..7d98eb6b 100644 --- a/src/add/fmul.py +++ b/src/add/fmul.py @@ -22,7 +22,7 @@ class FPMUL(FPBase): # Latches a = FPNum(self.width) b = FPNum(self.width) - z = FPNum(self.width, 24) + z = FPNum(self.width, False) tot = Signal(28) # sticky/round/guard bits, 23 result, 1 overflow @@ -259,4 +259,4 @@ always @(posedge clk) s_output_z_stb <= 0; end end - """ \ No newline at end of file + """ diff --git a/src/add/fpbase.py b/src/add/fpbase.py index 01bf3faa..c10e5d9b 100644 --- a/src/add/fpbase.py +++ b/src/add/fpbase.py @@ -17,22 +17,28 @@ class FPNum: (m[-1]) is effectively a carry-overflow. The other three are guard (m[2]), round (m[1]), and sticky (m[0]) """ - def __init__(self, width, m_width=None): + def __init__(self, width, m_extra=True): self.width = width - if m_width is None: - m_width = width - 5 # mantissa extra bits (top,guard,round) + m_width = {32: 24, 64: 53}[width] + e_width = {32: 10, 64: 13}[width] + e_max = 1<<(e_width-3) + if m_extra: + # mantissa extra bits (top,guard,round) + m_width += 3 + print (m_width, e_width, e_max) self.m_width = m_width + self.e_width = e_width self.v = Signal(width) # Latched copy of value self.m = Signal(m_width) # Mantissa - self.e = Signal((10, True)) # Exponent: 10 bits, signed + self.e = Signal((e_width, True)) # Exponent: 10 bits, signed self.s = Signal() # Sign bit self.mzero = Const(0, (m_width, False)) self.m1s = Const(-1, (m_width, False)) - self.P128 = Const(128, (10, True)) - self.P127 = Const(127, (10, True)) - self.N127 = Const(-127, (10, True)) - self.N126 = Const(-126, (10, True)) + self.P128 = Const(e_max, (e_width, True)) + self.P127 = Const(e_max-1, (e_width, True)) + self.N127 = Const(-(e_max-1), (e_width, True)) + self.N126 = Const(-(e_max-2), (e_width, True)) def decode(self, v): """ decodes a latched value into sign / exponent / mantissa diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index ddd7ad07..efb0c8bf 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -26,7 +26,7 @@ class FPADD(FPBase): # Latches a = FPNum(self.width) b = FPNum(self.width) - z = FPNum(self.width, 24) + z = FPNum(self.width, False) tot = Signal(28) # sticky/round/guard bits, 23 result, 1 overflow diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py index 1cbabd9e..918713a0 100644 --- a/src/add/nmigen_div_experiment.py +++ b/src/add/nmigen_div_experiment.py @@ -42,9 +42,9 @@ class FPDIV(FPBase): m = Module() # Latches - a = FPNum(self.width, 24) - b = FPNum(self.width, 24) - z = FPNum(self.width, 24) + a = FPNum(self.width, False) + b = FPNum(self.width, False) + z = FPNum(self.width, False) div = Div(51) -- 2.30.2