From 25a3be459084c12b2cbb44fd1ca2a5d0754cd0a3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Oct 2018 07:57:42 +0100 Subject: [PATCH] forgot to mask off data being written within element --- riscv/sv_insn_redirect.cc | 20 +++++++++++--------- riscv/sv_reg.h | 4 ++++ 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index 6e38eaf..5eb4f07 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -100,20 +100,21 @@ void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value) int bitwidth = get_bitwidth(_insn->reg_elwidth(reg, true), xlen); unsigned int shift = 0; unsigned int offs = 0; - if (spec.offset) { + if (spec.offset != NULL) { unsigned int nbytes = xlen / bitwidth; offs = *spec.offset; shift = offs % nbytes; offs /= nbytes; - fprintf(stderr, "writereg spec %ld bitwidth %d offs %d shift %d\n", - spec.reg, bitwidth, offs, shift); reg += offs; + fprintf(stderr, "writereg spec %ld %lx bitwidth %d offs %d shift %d\n", + reg, wval, bitwidth, offs, shift); } if (xlen != bitwidth) { uint64_t data = _insn->p->get_state()->XPR[reg]; uint64_t mask = ((1UL<reg_elwidth(reg, true), xlen); int shift = 0; int offs = 0; - if (spec.offset && spec.reg != 2) { // XXX HACK on spec.reg != 2 + if (spec.offset != NULL && spec.reg != 2) { // XXX HACK on spec.reg != 2 int nbytes = xlen / bitwidth; offs = *spec.offset; shift = offs % nbytes; @@ -260,7 +261,7 @@ sv_sreg_t (sv_proc_t::sext32)(sv_reg_t const& v) { uint64_t x = v; x = ((sreg_t)(int32_t)(x)); - return sv_sreg_t((int64_t)x); + return sv_sreg_t((int64_t)x, v.get_xlen(), v.get_elwidth()); } //sv_sreg_t (sv_proc_t::sext32)(sv_sreg_t const& v) @@ -345,8 +346,8 @@ sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs) { uint8_t bitwidth = _insn->src_bitwidth; if (bitwidth == xlen) { - //fprintf(stderr, "add result %lx %lx %lx\n", - // (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(lhs + rhs)); + fprintf(stderr, "add result %lx %lx %lx\n", + (uint64_t)lhs, (uint64_t)rhs, (uint64_t)(lhs + rhs)); return lhs + rhs; } uint64_t vlhs = 0; @@ -368,7 +369,8 @@ sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs) result = zext_bwid(result, bitwidth); } uint8_t reswidth = maxelwidth(lhs.get_elwidth(), rhs.get_elwidth()); - //fprintf(stderr, "add result %ld\n", result); + fprintf(stderr, "add result sext %d wid %d %lx\n", _insn->signextended, + reswidth, result); return sv_reg_t(result, xlen, reswidth); // XXX TODO: bitwidth } diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h index 5dfcb35..8bdc940 100644 --- a/riscv/sv_reg.h +++ b/riscv/sv_reg.h @@ -60,6 +60,10 @@ public: sv_sreg_t(int64_t _reg) : sv_regbase_t(), reg(_reg) {} // default elwidth sv_sreg_t(int64_t _reg, uint8_t _elwidth) : sv_regbase_t(_elwidth), reg(_reg) {} + sv_sreg_t(uint64_t _reg, int xlen, uint8_t _elwidth) : + sv_regbase_t(xlen, _elwidth), reg(_reg) + {} + int64_t reg; public: -- 2.30.2