From 25ba82d03178c4d8c1712517224dcd0745f230d7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 10 Jun 2021 12:30:37 +0100 Subject: [PATCH] power shuffle, split SDRAM --- 180nm_Oct2020/ls180.mdwn | 246 +++++++++++++++++++-------------------- 1 file changed, 123 insertions(+), 123 deletions(-) diff --git a/180nm_Oct2020/ls180.mdwn b/180nm_Oct2020/ls180.mdwn index 702c7f745..48a3225f3 100644 --- a/180nm_Oct2020/ls180.mdwn +++ b/180nm_Oct2020/ls180.mdwn @@ -26,12 +26,12 @@ auto-generated by [[pinouts.py]] | Pin | Mux0 | Mux1 | Mux2 | Mux3 | | --- | ----------- | ----------- | ----------- | ----------- | -| 32 | E GPIOE_E0 | | -| 33 | E GPIOE_E1 | | -| 34 | E GPIOE_E2 | | -| 35 | E GPIOE_E3 | | -| 36 | E GPIOE_E4 | | -| 37 | E SYS_PLLVCOUT | | +| 32 | E SYS_PLLVCOUT | | +| 33 | E GPIOE_E0 | | +| 34 | E GPIOE_E1 | | +| 35 | E GPIOE_E2 | | +| 36 | E GPIOE_E3 | | +| 37 | E GPIOE_E4 | | | 38 | E VSSI_4 | | | 39 | E VDDI_4 | | | 40 | E VDDI_4 | | @@ -67,46 +67,46 @@ auto-generated by [[pinouts.py]] | 65 | S VSSE_0 | | | 66 | S VDDI_0 | | | 67 | S VSSI_0 | | -| 68 | S SDR_DQM0 | | -| 69 | S SDR_D0 | | -| 70 | S SDR_D1 | | -| 71 | S SDR_D2 | | -| 72 | S SDR_D3 | | -| 73 | S SDR_D4 | | -| 74 | S SDR_D5 | | -| 75 | S SDR_D6 | | -| 76 | S SDR_D7 | | -| 77 | S SDR_AD0 | | -| 78 | S SDR_AD1 | | -| 79 | S SDR_AD2 | | -| 80 | S SDR_AD3 | | -| 81 | S SDR_AD4 | | -| 82 | S SDR_AD5 | | -| 83 | S SDR_AD6 | | -| 84 | S SDR_AD7 | | -| 85 | S SDR_AD8 | | -| 86 | S SDR_AD9 | | -| 87 | S SDR_BA0 | | -| 88 | S SDR_BA1 | | -| 90 | S MTWI_SDA | | -| 91 | S MTWI_SCL | | -| 92 | S VSSI_1 | | -| 93 | S VDDI_1 | | -| 94 | S VSSE_1 | | -| 95 | S VDDE_1 | | +| 68 | S MTWI_SDA | | +| 69 | S MTWI_SCL | | +| 70 | S SDR_DQM0 | | +| 71 | S SDR_D0 | | +| 72 | S SDR_D1 | | +| 73 | S SDR_D2 | | +| 74 | S SDR_D3 | | +| 75 | S SDR_D4 | | +| 76 | S SDR_D5 | | +| 77 | S SDR_D6 | | +| 78 | S SDR_D7 | | +| 79 | S SDR_BA0 | | +| 80 | S SDR_BA1 | | +| 81 | S SDR_AD0 | | +| 82 | S SDR_AD1 | | +| 83 | S SDR_AD2 | | +| 84 | S SDR_AD3 | | +| 86 | S VSSI_1 | | +| 87 | S VDDI_1 | | +| 88 | S VSSE_1 | | +| 89 | S VDDE_1 | | +| 90 | S SDR_AD4 | | +| 91 | S SDR_AD5 | | +| 92 | S SDR_AD6 | | +| 93 | S SDR_AD7 | | +| 94 | S SDR_AD8 | | +| 95 | S SDR_AD9 | | ## Bank W (32 pins, width 2) | Pin | Mux0 | Mux1 | Mux2 | Mux3 | | --- | ----------- | ----------- | ----------- | ----------- | -| 96 | W VDDE_2 | | -| 97 | W VSSE_2 | | -| 98 | W VDDI_2 | | -| 99 | W VSSI_2 | | -| 100 | W SDR_AD10 | | -| 101 | W SDR_AD11 | | -| 102 | W SDR_AD12 | | -| 103 | W SDR_DQM1 | | +| 96 | W SDR_AD10 | | +| 97 | W SDR_AD11 | | +| 98 | W SDR_AD12 | | +| 99 | W SDR_DQM1 | | +| 100 | W VDDE_2 | | +| 101 | W VSSE_2 | | +| 102 | W VDDI_2 | | +| 103 | W VSSI_2 | | | 104 | W SDR_D8 | | | 105 | W SDR_D9 | | | 106 | W SDR_D10 | | @@ -150,17 +150,17 @@ External Interrupt GPIO -* GPIOE_E0 : E0/0 -* GPIOE_E1 : E1/0 +* GPIOE_E0 : E1/0 +* GPIOE_E1 : E2/0 * GPIOE_E10 : E19/0 * GPIOE_E11 : E20/0 * GPIOE_E12 : E21/0 * GPIOE_E13 : E26/0 * GPIOE_E14 : E27/0 * GPIOE_E15 : E28/0 -* GPIOE_E2 : E2/0 -* GPIOE_E3 : E3/0 -* GPIOE_E4 : E4/0 +* GPIOE_E2 : E3/0 +* GPIOE_E3 : E4/0 +* GPIOE_E4 : E5/0 * GPIOE_E5 : E10/0 * GPIOE_E6 : E11/0 * GPIOE_E7 : E12/0 @@ -189,50 +189,50 @@ SPI Master 1 (general) I2C Master 1 -* MTWI_SCL : S27/0 -* MTWI_SDA : S26/0 +* MTWI_SCL : S5/0 +* MTWI_SDA : S4/0 ## SDR SDRAM -* SDR_AD0 : S13/0 -* SDR_AD1 : S14/0 -* SDR_AD10 : W4/0 -* SDR_AD11 : W5/0 -* SDR_AD12 : W6/0 -* SDR_AD2 : S15/0 -* SDR_AD3 : S16/0 -* SDR_AD4 : S17/0 -* SDR_AD5 : S18/0 -* SDR_AD6 : S19/0 -* SDR_AD7 : S20/0 -* SDR_AD8 : S21/0 -* SDR_AD9 : S22/0 -* SDR_BA0 : S23/0 -* SDR_BA1 : S24/0 +* SDR_AD0 : S17/0 +* SDR_AD1 : S18/0 +* SDR_AD10 : W0/0 +* SDR_AD11 : W1/0 +* SDR_AD12 : W2/0 +* SDR_AD2 : S19/0 +* SDR_AD3 : S20/0 +* SDR_AD4 : S26/0 +* SDR_AD5 : S27/0 +* SDR_AD6 : S28/0 +* SDR_AD7 : S29/0 +* SDR_AD8 : S30/0 +* SDR_AD9 : S31/0 +* SDR_BA0 : S15/0 +* SDR_BA1 : S16/0 * SDR_CASn : W19/0 * SDR_CKE : W17/0 * SDR_CLK : W16/0 * SDR_CSn0 : W21/0 -* SDR_D0 : S5/0 -* SDR_D1 : S6/0 +* SDR_D0 : S7/0 +* SDR_D1 : S8/0 * SDR_D10 : W10/0 * SDR_D11 : W11/0 * SDR_D12 : W12/0 * SDR_D13 : W13/0 * SDR_D14 : W14/0 * SDR_D15 : W15/0 -* SDR_D2 : S7/0 -* SDR_D3 : S8/0 -* SDR_D4 : S9/0 -* SDR_D5 : S10/0 -* SDR_D6 : S11/0 -* SDR_D7 : S12/0 +* SDR_D2 : S9/0 +* SDR_D3 : S10/0 +* SDR_D4 : S11/0 +* SDR_D5 : S12/0 +* SDR_D6 : S13/0 +* SDR_D7 : S14/0 * SDR_D8 : W8/0 * SDR_D9 : W9/0 -* SDR_DQM0 : S4/0 -* SDR_DQM1 : W7/0 +* SDR_DQM0 : S6/0 +* SDR_DQM1 : W3/0 * SDR_RASn : W18/0 * SDR_WEn : W20/0 @@ -244,7 +244,7 @@ System Control * SYS_PLLSELA0 : N29/0 * SYS_PLLSELA1 : N30/0 * SYS_PLLTESTOUT : N31/0 -* SYS_PLLVCOUT : E5/0 +* SYS_PLLVCOUT : E0/0 * SYS_RST : N27/0 ## UART0 @@ -259,13 +259,13 @@ UART (TX/RX) 1 Power * VDDE_0 : S0/0 -* VDDE_1 : S31/0 -* VDDE_2 : W0/0 +* VDDE_1 : S25/0 +* VDDE_2 : W4/0 * VDDE_3 : W25/0 * VDDE_6 : N7/0 * VDDI_0 : S2/0 -* VDDI_1 : S29/0 -* VDDI_2 : W2/0 +* VDDI_1 : S23/0 +* VDDI_2 : W6/0 * VDDI_3 : W23/0 * VDDI_4 : E7/0 E8/0 * VDDI_5 : E23/0 E25/0 @@ -277,13 +277,13 @@ Power GND * VSSE_0 : S1/0 -* VSSE_1 : S30/0 -* VSSE_2 : W1/0 +* VSSE_1 : S24/0 +* VSSE_2 : W5/0 * VSSE_3 : W24/0 * VSSE_6 : N6/0 * VSSI_0 : S3/0 -* VSSI_1 : S28/0 -* VSSI_2 : W3/0 +* VSSI_1 : S22/0 +* VSSI_2 : W7/0 * VSSI_3 : W22/0 * VSSI_4 : E6/0 E9/0 * VSSI_5 : E22/0 E24/0 @@ -304,11 +304,11 @@ GND ## GPIOE -* GPIOE_E0 32 E0/0 -* GPIOE_E1 33 E1/0 -* GPIOE_E2 34 E2/0 -* GPIOE_E3 35 E3/0 -* GPIOE_E4 36 E4/0 +* GPIOE_E0 33 E1/0 +* GPIOE_E1 34 E2/0 +* GPIOE_E2 35 E3/0 +* GPIOE_E3 36 E4/0 +* GPIOE_E4 37 E5/0 * GPIOE_E5 42 E10/0 * GPIOE_E6 43 E11/0 * GPIOE_E7 44 E12/0 @@ -362,15 +362,15 @@ GND * SYS_PLLSELA0 29 N29/0 * SYS_PLLSELA1 30 N30/0 * SYS_PLLTESTOUT 31 N31/0 -* SYS_PLLVCOUT 37 E5/0 +* SYS_PLLVCOUT 32 E0/0 ## MTWI I2C. -* MTWI_SDA 90 S26/0 -* MTWI_SCL 91 S27/0 +* MTWI_SDA 68 S4/0 +* MTWI_SCL 69 S5/0 ## MSPI0 @@ -383,31 +383,31 @@ I2C. -* SDR_DQM0 68 S4/0 -* SDR_D0 69 S5/0 -* SDR_D1 70 S6/0 -* SDR_D2 71 S7/0 -* SDR_D3 72 S8/0 -* SDR_D4 73 S9/0 -* SDR_D5 74 S10/0 -* SDR_D6 75 S11/0 -* SDR_D7 76 S12/0 -* SDR_AD0 77 S13/0 -* SDR_AD1 78 S14/0 -* SDR_AD2 79 S15/0 -* SDR_AD3 80 S16/0 -* SDR_AD4 81 S17/0 -* SDR_AD5 82 S18/0 -* SDR_AD6 83 S19/0 -* SDR_AD7 84 S20/0 -* SDR_AD8 85 S21/0 -* SDR_AD9 86 S22/0 -* SDR_BA0 87 S23/0 -* SDR_BA1 88 S24/0 -* SDR_AD10 100 W4/0 -* SDR_AD11 101 W5/0 -* SDR_AD12 102 W6/0 -* SDR_DQM1 103 W7/0 +* SDR_DQM0 70 S6/0 +* SDR_D0 71 S7/0 +* SDR_D1 72 S8/0 +* SDR_D2 73 S9/0 +* SDR_D3 74 S10/0 +* SDR_D4 75 S11/0 +* SDR_D5 76 S12/0 +* SDR_D6 77 S13/0 +* SDR_D7 78 S14/0 +* SDR_BA0 79 S15/0 +* SDR_BA1 80 S16/0 +* SDR_AD0 81 S17/0 +* SDR_AD1 82 S18/0 +* SDR_AD2 83 S19/0 +* SDR_AD3 84 S20/0 +* SDR_AD4 90 S26/0 +* SDR_AD5 91 S27/0 +* SDR_AD6 92 S28/0 +* SDR_AD7 93 S29/0 +* SDR_AD8 94 S30/0 +* SDR_AD9 95 S31/0 +* SDR_AD10 96 W0/0 +* SDR_AD11 97 W1/0 +* SDR_AD12 98 W2/0 +* SDR_DQM1 99 W3/0 * SDR_D8 104 W8/0 * SDR_D9 105 W9/0 * SDR_D10 106 W10/0 @@ -437,14 +437,14 @@ I2C. | 65 | S VSSE_0 | | | | | 66 | S VDDI_0 | | | | | 67 | S VSSI_0 | | | | -| 92 | S VSSI_1 | | | | -| 93 | S VDDI_1 | | | | -| 94 | S VSSE_1 | | | | -| 95 | S VDDE_1 | | | | -| 96 | W VDDE_2 | | | | -| 97 | W VSSE_2 | | | | -| 98 | W VDDI_2 | | | | -| 99 | W VSSI_2 | | | | +| 86 | S VSSI_1 | | | | +| 87 | S VDDI_1 | | | | +| 88 | S VSSE_1 | | | | +| 89 | S VDDE_1 | | | | +| 100 | W VDDE_2 | | | | +| 101 | W VSSE_2 | | | | +| 102 | W VDDI_2 | | | | +| 103 | W VSSI_2 | | | | | 118 | W VSSI_3 | | | | | 119 | W VDDI_3 | | | | | 120 | W VSSE_3 | | | | -- 2.30.2