From 25c585e8b736bc276b464930df6e753f2f63bdda Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 11 Sep 2020 15:23:57 +0100 Subject: [PATCH] WAY_BITS not TLB_WAY_BITS --- src/soc/experiment/dcache.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 97ca0761..ba16779b 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -637,7 +637,7 @@ class DCache(Elaboratable): with m.If(TLB_NUM_WAYS > 1): for i in range(TLB_SET_SIZE): # TLB PLRU interface - tlb_plru = PLRU(TLB_WAY_BITS) + tlb_plru = PLRU(WAY_BITS) setattr(m.submodules, "maybe_plru_%d" % i, tlb_plru) tlb_plru_acc = Signal(TLB_WAY_BITS) tlb_plru_acc_en = Signal() @@ -753,7 +753,7 @@ class DCache(Elaboratable): for i in range(NUM_LINES): # PLRU interface - plru = PLRU(TLB_WAY_BITS) + plru = PLRU(WAY_BITS) setattr(m.submodules, "plru%d" % i, plru) plru_acc = Signal(WAY_BITS) plru_acc_en = Signal() -- 2.30.2