From 25db6609b1b399ced761e8d9deeaf9560c942437 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 6 Apr 2019 03:46:03 +0100 Subject: [PATCH] rename p_o_ready to d_ready --- src/add/singlepipe.py | 2 +- src/add/test_buf_pipe.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index 7f3abc21..42b20654 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -530,7 +530,7 @@ class ControlBase: return m # intercept the previous (outgoing) "ready", combine with stage ready - m.d.comb += self.p.s_o_ready.eq(self.p._o_ready & self.stage.p_o_ready) + m.d.comb += self.p.s_o_ready.eq(self.p._o_ready & self.stage.d_ready) # intercept the next (incoming) "ready" and combine it with data valid m.d.comb += self.n.d_valid.eq(self.n.i_ready & self.stage.d_valid) diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index 29d30a88..82c8ff79 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -597,7 +597,7 @@ class ExampleStageDelayCls(StageCls): return Signal(16, name="example_output_signal") @property - def p_o_ready(self): + def d_ready(self): return Const(1) return self.count == 2 -- 2.30.2