From 25e0ccae9a74e8035b218a73c8c9c442f8a58aec Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 28 Oct 2014 11:30:15 +0100 Subject: [PATCH] remove DRP ports (won't be used for now) --- lib/sata/k7sataphy/crg.py | 28 ++-------------------------- lib/sata/k7sataphy/gtx.py | 16 +++++++--------- lib/sata/k7sataphy/std.py | 13 ------------- 3 files changed, 9 insertions(+), 48 deletions(-) diff --git a/lib/sata/k7sataphy/crg.py b/lib/sata/k7sataphy/crg.py index 5a0c2394..93ac490a 100644 --- a/lib/sata/k7sataphy/crg.py +++ b/lib/sata/k7sataphy/crg.py @@ -7,22 +7,6 @@ from migen.genlib.fsm import FSM, NextState from lib.sata.k7sataphy.std import * from lib.sata.k7sataphy.gtx import GTXE2_COMMON -class K7SATAPHYReconfig(Module): - def __init__(self, channel_drp, mmcm_drp): - self.speed = Signal(3) - - ### - - drp_sel = Signal() - drp = DRPBus() - self.comb += \ - If(drp_sel, - drp.connect(mmcm_drp) - ).Else( - drp.connect(channel_drp) - ) - # Todo - class K7SATAPHYCRG(Module): def __init__(self, pads, gtx, clk_freq, default_speed): self.reset = Signal() @@ -34,9 +18,6 @@ class K7SATAPHYCRG(Module): # CPLL # (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps # (SATA2 & SATA1) VCO still @ 3 GHz, Line rate is decreased with output dividers. - # When changing rate, reconfiguration of the CPLL over DRP is needed to: - # - update the output divider - # - update the equalizer configuration (specific for each line rate). refclk = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=0, @@ -60,10 +41,8 @@ class K7SATAPHYCRG(Module): # (SATA3) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 300MHz (16-bits) # (SATA2) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 150MHz (16-bits) # (SATA1) 150MHz from CPLL TXOUTCLK, sata_tx clk @ 75MHz (16-bits) - # When changing rate, reconfiguration of the MMCM is needed to update the output divider. mmcm_reset = Signal() mmcm_locked = Signal() - mmcm_drp = DRPBus() mmcm_fb = Signal() mmcm_clk_i = Signal() mmcm_clk0_o = Signal() @@ -79,8 +58,8 @@ class K7SATAPHYCRG(Module): p_BANDWIDTH="HIGH", p_COMPENSATION="ZHOLD", i_RST=mmcm_reset, o_LOCKED=mmcm_locked, # DRP - i_DCLK=mmcm_drp.clk, i_DEN=mmcm_drp.en, o_DRDY=mmcm_drp.rdy, i_DWE=mmcm_drp.we, - i_DADDR=mmcm_drp.addr, i_DI=mmcm_drp.di, o_DO=mmcm_drp.do, + i_DCLK=0, i_DEN=0, i_DWE=0, #o_DRDY=, + i_DADDR=0, i_DI=0, #o_DO=, # VCO p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=6.666, @@ -191,6 +170,3 @@ class K7SATAPHYCRG(Module): AsyncResetSynchronizer(self.cd_sata_tx, ~self.tx_ready), AsyncResetSynchronizer(self.cd_sata_rx, ~self.rx_ready), ] - - # Dynamic Reconfiguration - self.submodules.reconfig = K7SATAPHYReconfig(mmcm_drp, gtx.drp) diff --git a/lib/sata/k7sataphy/gtx.py b/lib/sata/k7sataphy/gtx.py index 65fff921..982cbb9a 100644 --- a/lib/sata/k7sataphy/gtx.py +++ b/lib/sata/k7sataphy/gtx.py @@ -14,8 +14,6 @@ class _PulseSynchronizer(PulseSynchronizer): class K7SATAPHYGTX(Module): def __init__(self, pads, default_speed): # Interface - self.drp = DRPBus() - # Channel - Ref Clock Ports self.gtrefclk0 = Signal() @@ -468,13 +466,13 @@ class K7SATAPHYGTX(Module): i_GTSOUTHREFCLK1=0, # Channel - DRP Ports - i_DRPADDR=self.drp.addr, - i_DRPCLK=self.drp.clk, - i_DRPDI=self.drp.di, - o_DRPDO=self.drp.do, - i_DRPEN=self.drp.en, - o_DRPRDY=self.drp.rdy, - i_DRPWE=self.drp.we, + i_DRPADDR=0, + i_DRPCLK=0, + i_DRPDI=0, + #o_DRPDO=, + i_DRPEN=0, + #o_DRPRDY=, + i_DRPWE=0, # Clocking Ports #o_GTREFCLKMONITOR=, diff --git a/lib/sata/k7sataphy/std.py b/lib/sata/k7sataphy/std.py index 8417a118..5a218990 100644 --- a/lib/sata/k7sataphy/std.py +++ b/lib/sata/k7sataphy/std.py @@ -6,16 +6,3 @@ SYNC_VAL = 0xB5B5957C def ones(width): return 2**width-1 - -class DRPBus(Record): - def __init__(self): - layout = [ - ("clk", 1, DIR_M_TO_S), - ("en", 1, DIR_M_TO_S), - ("rdy", 1, DIR_S_TO_M), - ("we", 1, DIR_M_TO_S), - ("addr", 8, DIR_M_TO_S), - ("di", 16, DIR_M_TO_S), - ("do", 16, DIR_S_TO_M) - ] - Record.__init__(self, layout) -- 2.30.2