From 25e807cccfd0dd8cbc996d98c2931b10d4443cd1 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 27 Jan 2020 09:51:37 -0500 Subject: [PATCH] Add more/better comments to fsignj.py --- src/ieee754/fsgnj/fsgnj.py | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/ieee754/fsgnj/fsgnj.py b/src/ieee754/fsgnj/fsgnj.py index 31501743..be6060bd 100644 --- a/src/ieee754/fsgnj/fsgnj.py +++ b/src/ieee754/fsgnj/fsgnj.py @@ -36,8 +36,8 @@ class FSGNJPipeMod(PipeModBase): comb = m.d.comb z1 = self.o.z - a = self.i.a - b = self.i.b + + # Decode the input operands into sign, exponent, and mantissa a1 = FPNumBaseRecord(width, False) b1 = FPNumBaseRecord(width, False) m.submodules.sc_decode_a = a1 = FPNumDecode(None, a1) @@ -47,12 +47,22 @@ class FSGNJPipeMod(PipeModBase): opcode = self.i.ctx.op - sign = Signal() + # Calculate the sign bit + sign = Signal(reset_less=True) + + # Handle opcodes 0b00 and 0b01, copying or inverting the sign bit of B sign = Mux(opcode[0], ~b1.s, b1.s) - sign = Mux(opcode[1], sign ^ a1.s, sign) + # Handle opcodes 0b10 and 0b11, XORing the sign bits of a and b together. + # opcode 0b11 is not defined in the RISCV spec; it is handled + # here as equivalent to opcode 0b10 (i.e. a1.s XOR b1.s) + # because this requires slightly less logic than making it the + # same as opcode 0b00 (1 less Mux). + sign = Mux(opcode[1], b1.s ^ a1.s, sign) + # Create the floating point number from the sign bit + # calculated earlier and the exponent and mantissa of operand a comb += z1.eq(a1.fp.create2(sign, a1.e, a1.m)) # copy the context (muxid, operator) -- 2.30.2