From 25f0a2b63056e9fbb2a12b063e3c19cc1d3a8983 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 14 May 2022 01:26:25 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 5e5ca12ca..bc3eeb677 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -605,10 +605,10 @@ out to an entirely different loop, all based on conditions determined dynamically at runtime. Even when deployed on as basic a CPU as a single-issue in-order RISC -core, the performance and power-savings were astonishing: between 20 -and **80%** reduction in algorithm completion times were achieved compared +core, the performance and power-savings were astonishing: between 27 +and **75%** reduction in algorithm completion times were achieved compared to a more traditional branch-speculative in-order RISC CPU. MPEG -Decode, the target algorithm specifically picked by the researcher +Encode's timing, the target algorithm specifically picked by the researcher due to its high complexity with 6-deep nested loops and conditional execution that frequently jumped in and out of at least 2 loops, came out with an astonishing 43% improvement in completion time. 43% -- 2.30.2