From 25fddab0a77fae96986a0d75f6bbe9ad65060476 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 16 May 2020 19:26:25 +0100 Subject: [PATCH] add debug info of what instruction was executed and Asserted --- src/soc/cr/test/test_pipe_caller.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/cr/test/test_pipe_caller.py b/src/soc/cr/test/test_pipe_caller.py index ccb41a76..ef90ddca 100644 --- a/src/soc/cr/test/test_pipe_caller.py +++ b/src/soc/cr/test/test_pipe_caller.py @@ -186,6 +186,7 @@ class TestRunner(FHDLTestCase): cr_expected = simulator.cr.get_range().value cr_real = yield alu.n.data_o.cr msg = f"real: {cr_expected:x}, actual: {cr_real:x}" + msg += " code: %s" % code self.assertEqual(cr_expected, cr_real, msg) sim.add_sync_process(process) -- 2.30.2