From 260ef9c9bec8695d5988a91443988516d39d0240 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 24 Feb 2016 00:54:11 +0100 Subject: [PATCH] gallium/radeon: use a structure for passing tiling flags from/to winsys MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit and call it radeon_bo_metadata Reviewed-by: Michel Dänzer Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/r300/r300_texture.c | 22 +++--- src/gallium/drivers/radeon/r600_texture.c | 52 +++++++------- src/gallium/drivers/radeon/radeon_winsys.h | 50 +++++++------- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 59 ++++++---------- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 68 +++++++------------ 5 files changed, 109 insertions(+), 142 deletions(-) diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 2b9018a5de3..81929632daf 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -1006,6 +1006,7 @@ r300_texture_create_object(struct r300_screen *rscreen, { struct radeon_winsys *rws = rscreen->rws; struct r300_resource *tex = NULL; + struct radeon_bo_metadata tiling = {}; tex = CALLOC_STRUCT(r300_resource); if (!tex) { @@ -1060,10 +1061,10 @@ r300_texture_create_object(struct r300_screen *rscreen, util_format_is_depth_or_stencil(base->format) ? "depth" : "color"); } - rws->buffer_set_tiling(tex->buf, NULL, - tex->tex.microtile, tex->tex.macrotile[0], - 0, 0, 0, 0, 0, 0, 0, - tex->tex.stride_in_bytes[0], false); + tiling.microtile = tex->tex.microtile; + tiling.macrotile = tex->tex.macrotile[0]; + tiling.stride = tex->tex.stride_in_bytes[0]; + rws->buffer_set_tiling(tex->buf, NULL, &tiling); return tex; @@ -1104,8 +1105,8 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, struct r300_screen *rscreen = r300_screen(screen); struct radeon_winsys *rws = rscreen->rws; struct pb_buffer *buffer; - enum radeon_bo_layout microtile, macrotile; unsigned stride; + struct radeon_bo_metadata tiling = {}; /* Support only 2D textures without mipmaps */ if ((base->target != PIPE_TEXTURE_2D && @@ -1119,25 +1120,24 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, if (!buffer) return NULL; - rws->buffer_get_tiling(buffer, µtile, ¯otile, NULL, NULL, NULL, - NULL, NULL, NULL); + rws->buffer_get_tiling(buffer, &tiling); /* Enforce a microtiled zbuffer. */ if (util_format_is_depth_or_stencil(base->format) && - microtile == RADEON_LAYOUT_LINEAR) { + tiling.microtile == RADEON_LAYOUT_LINEAR) { switch (util_format_get_blocksize(base->format)) { case 4: - microtile = RADEON_LAYOUT_TILED; + tiling.microtile = RADEON_LAYOUT_TILED; break; case 2: - microtile = RADEON_LAYOUT_SQUARETILED; + tiling.microtile = RADEON_LAYOUT_SQUARETILED; break; } } return (struct pipe_resource*) - r300_texture_create_object(rscreen, base, microtile, macrotile, + r300_texture_create_object(rscreen, base, tiling.microtile, tiling.macrotile, stride, buffer); } diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index e441936b447..f3087ce3046 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -237,20 +237,23 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen, struct r600_resource *resource = &rtex->resource; struct radeon_surf *surface = &rtex->surface; struct r600_common_screen *rscreen = (struct r600_common_screen*)screen; - - rscreen->ws->buffer_set_tiling(resource->buf, - NULL, - surface->level[0].mode >= RADEON_SURF_MODE_1D ? - RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, - surface->level[0].mode >= RADEON_SURF_MODE_2D ? - RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, - surface->pipe_config, - surface->bankw, surface->bankh, - surface->tile_split, - surface->stencil_tile_split, - surface->mtilea, surface->num_banks, - surface->level[0].pitch_bytes, - (surface->flags & RADEON_SURF_SCANOUT) != 0); + struct radeon_bo_metadata metadata = {}; + + metadata.microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ? + RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; + metadata.macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ? + RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR; + metadata.pipe_config = surface->pipe_config; + metadata.bankw = surface->bankw; + metadata.bankh = surface->bankh; + metadata.tile_split = surface->tile_split; + metadata.stencil_tile_split = surface->stencil_tile_split; + metadata.mtilea = surface->mtilea; + metadata.num_banks = surface->num_banks; + metadata.stride = surface->level[0].pitch_bytes; + metadata.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0; + + rscreen->ws->buffer_set_tiling(resource->buf, NULL, &metadata); return rscreen->ws->buffer_get_handle(resource->buf, surface->level[0].pitch_bytes, whandle); @@ -885,10 +888,9 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen struct pb_buffer *buf = NULL; unsigned stride = 0; unsigned array_mode; - enum radeon_bo_layout micro, macro; struct radeon_surf surface; - bool scanout; int r; + struct radeon_bo_metadata metadata = {}; /* Support only 2D textures without mipmaps */ if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || @@ -899,15 +901,17 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen if (!buf) return NULL; - rscreen->ws->buffer_get_tiling(buf, µ, ¯o, - &surface.bankw, &surface.bankh, - &surface.tile_split, - &surface.stencil_tile_split, - &surface.mtilea, &scanout); + rscreen->ws->buffer_get_tiling(buf, &metadata); + + surface.bankw = metadata.bankw; + surface.bankh = metadata.bankh; + surface.tile_split = metadata.tile_split; + surface.stencil_tile_split = metadata.stencil_tile_split; + surface.mtilea = metadata.mtilea; - if (macro == RADEON_LAYOUT_TILED) + if (metadata.macrotile == RADEON_LAYOUT_TILED) array_mode = RADEON_SURF_MODE_2D; - else if (micro == RADEON_LAYOUT_TILED) + else if (metadata.microtile == RADEON_LAYOUT_TILED) array_mode = RADEON_SURF_MODE_1D; else array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; @@ -917,7 +921,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen return NULL; } - if (scanout) + if (metadata.scanout) surface.flags |= RADEON_SURF_SCANOUT; return (struct pipe_resource *)r600_texture_create_object(screen, templ, diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 1160d235062..5aaa80d4a1e 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -276,6 +276,21 @@ struct radeon_info { uint32_t cik_macrotile_mode_array[16]; }; +/* Tiling info for display code, DRI sharing, and other data. */ +struct radeon_bo_metadata { + enum radeon_bo_layout microtile; + enum radeon_bo_layout macrotile; + unsigned pipe_config; + unsigned bankw; + unsigned bankh; + unsigned tile_split; + unsigned stencil_tile_split; + unsigned mtilea; + unsigned num_banks; + unsigned stride; + bool scanout; +}; + enum radeon_feature_id { RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */ RADEON_FID_R300_CMASK_ACCESS, @@ -454,45 +469,26 @@ struct radeon_winsys { enum radeon_bo_usage usage); /** - * Return tiling flags describing a memory layout of a buffer object. + * Return buffer metadata. + * (tiling info for display code, DRI sharing, and other data) * * \param buf A winsys buffer object to get the flags from. - * \param macrotile A pointer to the return value of the microtile flag. - * \param microtile A pointer to the return value of the macrotile flag. - * - * \note microtile and macrotile are not bitmasks! + * \param md Metadata */ void (*buffer_get_tiling)(struct pb_buffer *buf, - enum radeon_bo_layout *microtile, - enum radeon_bo_layout *macrotile, - unsigned *bankw, unsigned *bankh, - unsigned *tile_split, - unsigned *stencil_tile_split, - unsigned *mtilea, - bool *scanout); + struct radeon_bo_metadata *md); /** - * Set tiling flags describing a memory layout of a buffer object. + * Set buffer metadata. + * (tiling info for display code, DRI sharing, and other data) * * \param buf A winsys buffer object to set the flags for. * \param cs A command stream to flush if the buffer is referenced by it. - * \param macrotile A macrotile flag. - * \param microtile A microtile flag. - * \param stride A stride of the buffer in bytes, for texturing. - * - * \note microtile and macrotile are not bitmasks! + * \param md Metadata */ void (*buffer_set_tiling)(struct pb_buffer *buf, struct radeon_winsys_cs *rcs, - enum radeon_bo_layout microtile, - enum radeon_bo_layout macrotile, - unsigned pipe_config, - unsigned bankw, unsigned bankh, - unsigned tile_split, - unsigned stencil_tile_split, - unsigned mtilea, unsigned num_banks, - unsigned stride, - bool scanout); + struct radeon_bo_metadata *md); /** * Get a winsys buffer from a winsys handle. The internal structure diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 59a801b1426..0ed9529a449 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -391,13 +391,7 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split) } static void amdgpu_bo_get_tiling(struct pb_buffer *_buf, - enum radeon_bo_layout *microtiled, - enum radeon_bo_layout *macrotiled, - unsigned *bankw, unsigned *bankh, - unsigned *tile_split, - unsigned *stencil_tile_split, - unsigned *mtilea, - bool *scanout) + struct radeon_bo_metadata *md) { struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); struct amdgpu_bo_info info = {0}; @@ -410,56 +404,45 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf, tiling_flags = info.metadata.tiling_info; - *microtiled = RADEON_LAYOUT_LINEAR; - *macrotiled = RADEON_LAYOUT_LINEAR; + md->microtile = RADEON_LAYOUT_LINEAR; + md->macrotile = RADEON_LAYOUT_LINEAR; if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */ - *macrotiled = RADEON_LAYOUT_TILED; + md->macrotile = RADEON_LAYOUT_TILED; else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */ - *microtiled = RADEON_LAYOUT_TILED; + md->microtile = RADEON_LAYOUT_TILED; - if (bankw && tile_split && mtilea && tile_split) { - *bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); - *bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); - *tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); - *mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); - } - if (scanout) - *scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */ + md->bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); + md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); + md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); + md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); + md->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */ } static void amdgpu_bo_set_tiling(struct pb_buffer *_buf, struct radeon_winsys_cs *rcs, - enum radeon_bo_layout microtiled, - enum radeon_bo_layout macrotiled, - unsigned pipe_config, - unsigned bankw, unsigned bankh, - unsigned tile_split, - unsigned stencil_tile_split, - unsigned mtilea, unsigned num_banks, - uint32_t pitch, - bool scanout) + struct radeon_bo_metadata *md) { struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); struct amdgpu_bo_metadata metadata = {0}; uint32_t tiling_flags = 0; - if (macrotiled == RADEON_LAYOUT_TILED) + if (md->macrotile == RADEON_LAYOUT_TILED) tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */ - else if (microtiled == RADEON_LAYOUT_TILED) + else if (md->microtile == RADEON_LAYOUT_TILED) tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */ else tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */ - tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, pipe_config); - tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(bankw)); - tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(bankh)); - if (tile_split) - tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(tile_split)); - tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(mtilea)); - tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(num_banks)-1); + tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->pipe_config); + tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw)); + tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh)); + if (md->tile_split) + tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(md->tile_split)); + tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea)); + tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->num_banks)-1); - if (scanout) + if (md->scanout) tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */ else tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */ diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 7e9ed0ca0fe..ce91af4486f 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -637,13 +637,7 @@ static unsigned eg_tile_split_rev(unsigned eg_tile_split) } static void radeon_bo_get_tiling(struct pb_buffer *_buf, - enum radeon_bo_layout *microtiled, - enum radeon_bo_layout *macrotiled, - unsigned *bankw, unsigned *bankh, - unsigned *tile_split, - unsigned *stencil_tile_split, - unsigned *mtilea, - bool *scanout) + struct radeon_bo_metadata *md) { struct radeon_bo *bo = radeon_bo(_buf); struct drm_radeon_gem_set_tiling args; @@ -657,38 +651,28 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf, &args, sizeof(args)); - *microtiled = RADEON_LAYOUT_LINEAR; - *macrotiled = RADEON_LAYOUT_LINEAR; + md->microtile = RADEON_LAYOUT_LINEAR; + md->macrotile = RADEON_LAYOUT_LINEAR; if (args.tiling_flags & RADEON_TILING_MICRO) - *microtiled = RADEON_LAYOUT_TILED; + md->microtile = RADEON_LAYOUT_TILED; else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE) - *microtiled = RADEON_LAYOUT_SQUARETILED; + md->microtile = RADEON_LAYOUT_SQUARETILED; if (args.tiling_flags & RADEON_TILING_MACRO) - *macrotiled = RADEON_LAYOUT_TILED; - if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) { - *bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; - *bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; - *tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; - *stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; - *mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; - *tile_split = eg_tile_split(*tile_split); - } - if (scanout) - *scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT); + md->macrotile = RADEON_LAYOUT_TILED; + + md->bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; + md->bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; + md->tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; + md->stencil_tile_split = (args.tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; + md->mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; + md->tile_split = eg_tile_split(md->tile_split); + md->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT); } static void radeon_bo_set_tiling(struct pb_buffer *_buf, struct radeon_winsys_cs *rcs, - enum radeon_bo_layout microtiled, - enum radeon_bo_layout macrotiled, - unsigned pipe_config, - unsigned bankw, unsigned bankh, - unsigned tile_split, - unsigned stencil_tile_split, - unsigned mtilea, unsigned num_banks, - uint32_t pitch, - bool scanout) + struct radeon_bo_metadata *md) { struct radeon_bo *bo = radeon_bo(_buf); struct radeon_drm_cs *cs = radeon_drm_cs(rcs); @@ -704,34 +688,34 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf, os_wait_until_zero(&bo->num_active_ioctls, PIPE_TIMEOUT_INFINITE); - if (microtiled == RADEON_LAYOUT_TILED) + if (md->microtile == RADEON_LAYOUT_TILED) args.tiling_flags |= RADEON_TILING_MICRO; - else if (microtiled == RADEON_LAYOUT_SQUARETILED) + else if (md->microtile == RADEON_LAYOUT_SQUARETILED) args.tiling_flags |= RADEON_TILING_MICRO_SQUARE; - if (macrotiled == RADEON_LAYOUT_TILED) + if (md->macrotile == RADEON_LAYOUT_TILED) args.tiling_flags |= RADEON_TILING_MACRO; - args.tiling_flags |= (bankw & RADEON_TILING_EG_BANKW_MASK) << + args.tiling_flags |= (md->bankw & RADEON_TILING_EG_BANKW_MASK) << RADEON_TILING_EG_BANKW_SHIFT; - args.tiling_flags |= (bankh & RADEON_TILING_EG_BANKH_MASK) << + args.tiling_flags |= (md->bankh & RADEON_TILING_EG_BANKH_MASK) << RADEON_TILING_EG_BANKH_SHIFT; - if (tile_split) { - args.tiling_flags |= (eg_tile_split_rev(tile_split) & + if (md->tile_split) { + args.tiling_flags |= (eg_tile_split_rev(md->tile_split) & RADEON_TILING_EG_TILE_SPLIT_MASK) << RADEON_TILING_EG_TILE_SPLIT_SHIFT; } - args.tiling_flags |= (stencil_tile_split & + args.tiling_flags |= (md->stencil_tile_split & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT; - args.tiling_flags |= (mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << + args.tiling_flags |= (md->mtilea & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK) << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT; - if (bo->rws->gen >= DRV_SI && !scanout) + if (bo->rws->gen >= DRV_SI && !md->scanout) args.tiling_flags |= RADEON_TILING_R600_NO_SCANOUT; args.handle = bo->handle; - args.pitch = pitch; + args.pitch = md->stride; drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_SET_TILING, -- 2.30.2