From 260fc34c975695777e3a1be905103b8dfe837595 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 18 May 2020 01:59:40 -0700 Subject: [PATCH] arch,cpu: Add a setThreadContext method to the ISA class. Also remove ThreadContext pointer parameters to some of the methods in the ISA classes. Change-Id: I8e502b1857d299cb2e759a9734a1df4f65f31efe Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29233 Reviewed-by: Brandon Potter Maintainer: Gabe Black Tested-by: kokoro --- src/arch/arm/insts/static_inst.cc | 2 +- src/arch/arm/isa.cc | 219 +++++++++++++++--------------- src/arch/arm/isa.hh | 33 ++--- src/arch/generic/isa.hh | 4 + src/arch/mips/isa.cc | 4 +- src/arch/mips/isa.hh | 62 ++------- src/arch/power/isa.hh | 21 +-- src/arch/riscv/isa.cc | 4 +- src/arch/riscv/isa.hh | 12 +- src/arch/sparc/isa.cc | 98 ++++--------- src/arch/sparc/isa.hh | 80 +++-------- src/arch/sparc/ua2005.cc | 32 ++--- src/arch/x86/isa.cc | 25 ++-- src/arch/x86/isa.hh | 58 ++------ src/cpu/SConscript | 1 - src/cpu/base.cc | 6 +- src/cpu/cpuevent.cc | 59 -------- src/cpu/cpuevent.hh | 90 ------------ src/cpu/kvm/base.cc | 2 - src/cpu/minor/cpu.cc | 4 +- src/cpu/o3/cpu.cc | 6 +- src/cpu/o3/thread_context_impl.hh | 2 +- src/cpu/simple/base.cc | 8 -- src/cpu/simple/base.hh | 2 - src/cpu/simple_thread.cc | 6 - src/cpu/simple_thread.hh | 7 +- 26 files changed, 245 insertions(+), 602 deletions(-) delete mode 100644 src/cpu/cpuevent.cc delete mode 100644 src/cpu/cpuevent.hh diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 9c686f6ca..9966b9ee5 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -1171,7 +1171,7 @@ unsigned ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc) { auto *isa = static_cast(tc->getIsaPtr()); - return isa->getCurSveVecLenInBits(tc); + return isa->getCurSveVecLenInBits(); } } diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index b3ea91ef4..29c553878 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -119,20 +119,17 @@ ISA::params() const return dynamic_cast(_params); } -void -ISA::clear(ThreadContext *tc) -{ - clear(); - // Invalidate cached copies of miscregs in the TLBs - getITBPtr(tc)->invalidateMiscReg(); - getDTBPtr(tc)->invalidateMiscReg(); -} - void ISA::clear() { const Params *p(params()); + // Invalidate cached copies of miscregs in the TLBs + if (tc) { + getITBPtr(tc)->invalidateMiscReg(); + getDTBPtr(tc)->invalidateMiscReg(); + } + SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; memset(miscRegs, 0, sizeof(miscRegs)); @@ -421,31 +418,40 @@ ISA::initID64(const ArmISAParams *p) } void -ISA::startup(ThreadContext *tc) +ISA::startup() { - pmu->setThreadContext(tc); + BaseISA::startup(); - if (system) { - Gicv3 *gicv3 = dynamic_cast(system->getGIC()); - if (gicv3) { - gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); - gicv3CpuInterface->setISA(this); - gicv3CpuInterface->setThreadContext(tc); - } - } + if (tc) + setupThreadContext(); afterStartup = true; } void -ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) +ISA::setupThreadContext() { - pmu->setThreadContext(new_tc); + pmu->setThreadContext(tc); - if (system && gicv3CpuInterface) { - gicv3CpuInterface->setISA(this); - gicv3CpuInterface->setThreadContext(new_tc); - } + if (!system) + return; + + Gicv3 *gicv3 = dynamic_cast(system->getGIC()); + if (!gicv3) + return; + + if (!gicv3CpuInterface) + gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); + + gicv3CpuInterface->setISA(this); + gicv3CpuInterface->setThreadContext(tc); +} + +void +ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) +{ + tc = new_tc; + setupThreadContext(); } RegVal @@ -473,7 +479,7 @@ ISA::readMiscRegNoEffect(int misc_reg) const RegVal -ISA::readMiscReg(int misc_reg, ThreadContext *tc) +ISA::readMiscReg(int misc_reg) { CPSR cpsr = 0; PCState pc = 0; @@ -760,12 +766,12 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) // Generic Timer registers case MISCREG_CNTFRQ ... MISCREG_CNTVOFF: case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2: - return getGenericTimer(tc).readMiscReg(misc_reg); + return getGenericTimer().readMiscReg(misc_reg); case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: - return getGICv3CPUInterface(tc).readMiscReg(misc_reg); + return getGICv3CPUInterface().readMiscReg(misc_reg); default: break; @@ -797,7 +803,7 @@ ISA::setMiscRegNoEffect(int misc_reg, RegVal val) } void -ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) +ISA::setMiscReg(int misc_reg, RegVal val) { RegVal newVal = val; @@ -827,7 +833,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) pc.nextJazelle(cpsr.j); pc.illegalExec(cpsr.il == 1); - tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); + tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1); // Follow slightly different semantics if a CheckerCPU object // is connected @@ -1132,8 +1138,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // TLB Invalidate All case MISCREG_TLBIALL: // TLBI all entries, EL0&1, { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); tlbiOp(tc); @@ -1142,8 +1148,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // TLB Invalidate All, Inner Shareable case MISCREG_TLBIALLIS: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); tlbiOp.broadcast(tc); @@ -1152,8 +1158,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // Instruction TLB Invalidate All case MISCREG_ITLBIALL: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); tlbiOp(tc); @@ -1162,8 +1168,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // Data TLB Invalidate All case MISCREG_DTLBIALL: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); tlbiOp(tc); @@ -1176,8 +1182,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBIMVA: case MISCREG_TLBIMVAL: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1191,8 +1197,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBIMVAIS: case MISCREG_TLBIMVALIS: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1205,8 +1211,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // TLB Invalidate by ASID match case MISCREG_TLBIASID: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1218,8 +1224,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // TLB Invalidate by ASID match, Inner Shareable case MISCREG_TLBIASIDIS: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1235,8 +1241,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBIMVAA: case MISCREG_TLBIMVAAL: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, mbits(newVal, 31,12)); @@ -1248,8 +1254,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBIMVAAIS: case MISCREG_TLBIMVAALIS: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, mbits(newVal, 31,12)); @@ -1264,8 +1270,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBIMVAH: case MISCREG_TLBIMVALH: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, mbits(newVal, 31,12)); @@ -1277,8 +1283,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBIMVAHIS: case MISCREG_TLBIMVALHIS: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, mbits(newVal, 31,12)); @@ -1293,8 +1299,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBIIPAS2: case MISCREG_TLBIIPAS2L: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1308,8 +1314,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBIIPAS2IS: case MISCREG_TLBIIPAS2LIS: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1321,8 +1327,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // Instruction TLB Invalidate by VA case MISCREG_ITLBIMVA: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); ITLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1335,8 +1341,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // Data TLB Invalidate by VA case MISCREG_DTLBIMVA: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); DTLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1349,8 +1355,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // Instruction TLB Invalidate by ASID match case MISCREG_ITLBIASID: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); ITLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1362,8 +1368,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // Data TLB Invalidate by ASID match case MISCREG_DTLBIASID: { - assert32(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert32(); + scr = readMiscReg(MISCREG_SCR); DTLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, @@ -1375,7 +1381,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // TLB Invalidate All, Non-Secure Non-Hyp case MISCREG_TLBIALLNSNH: { - assert32(tc); + assert32(); TLBIALLN tlbiOp(EL1); tlbiOp(tc); @@ -1384,7 +1390,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable case MISCREG_TLBIALLNSNHIS: { - assert32(tc); + assert32(); TLBIALLN tlbiOp(EL1); tlbiOp.broadcast(tc); @@ -1393,7 +1399,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // TLB Invalidate All, Hyp mode case MISCREG_TLBIALLH: { - assert32(tc); + assert32(); TLBIALLN tlbiOp(EL2); tlbiOp(tc); @@ -1402,7 +1408,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // TLB Invalidate All, Hyp mode, Inner Shareable case MISCREG_TLBIALLHIS: { - assert32(tc); + assert32(); TLBIALLN tlbiOp(EL2); tlbiOp.broadcast(tc); @@ -1411,7 +1417,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // AArch64 TLB Invalidate All, EL3 case MISCREG_TLBI_ALLE3: { - assert64(tc); + assert64(); TLBIALL tlbiOp(EL3, true); tlbiOp(tc); @@ -1420,7 +1426,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // AArch64 TLB Invalidate All, EL3, Inner Shareable case MISCREG_TLBI_ALLE3IS: { - assert64(tc); + assert64(); TLBIALL tlbiOp(EL3, true); tlbiOp.broadcast(tc); @@ -1430,8 +1436,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_ALLE2: case MISCREG_TLBI_ALLE2IS: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); tlbiOp(tc); @@ -1443,8 +1449,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VMALLS12E1: // @todo: handle VMID and stage 2 to enable Virtualization { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); tlbiOp(tc); @@ -1456,8 +1462,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VMALLS12E1IS: // @todo: handle VMID and stage 2 to enable Virtualization { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); tlbiOp.broadcast(tc); @@ -1471,7 +1477,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VAE3_Xt: case MISCREG_TLBI_VALE3_Xt: { - assert64(tc); + assert64(); TLBIMVA tlbiOp(EL3, true, static_cast(bits(newVal, 43, 0)) << 12, @@ -1483,7 +1489,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VAE3IS_Xt: case MISCREG_TLBI_VALE3IS_Xt: { - assert64(tc); + assert64(); TLBIMVA tlbiOp(EL3, true, static_cast(bits(newVal, 43, 0)) << 12, @@ -1496,8 +1502,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VAE2_Xt: case MISCREG_TLBI_VALE2_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, static_cast(bits(newVal, 43, 0)) << 12, @@ -1509,8 +1515,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VAE2IS_Xt: case MISCREG_TLBI_VALE2IS_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, static_cast(bits(newVal, 43, 0)) << 12, @@ -1523,8 +1529,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VAE1_Xt: case MISCREG_TLBI_VALE1_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : bits(newVal, 55, 48); @@ -1539,8 +1545,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VAE1IS_Xt: case MISCREG_TLBI_VALE1IS_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : bits(newVal, 55, 48); @@ -1555,8 +1561,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // @todo: handle VMID to enable Virtualization case MISCREG_TLBI_ASIDE1_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : bits(newVal, 55, 48); @@ -1567,8 +1573,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable case MISCREG_TLBI_ASIDE1IS_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : bits(newVal, 55, 48); @@ -1582,8 +1588,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VAAE1_Xt: case MISCREG_TLBI_VAALE1_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, static_cast(bits(newVal, 43, 0)) << 12); @@ -1595,8 +1601,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_VAAE1IS_Xt: case MISCREG_TLBI_VAALE1IS_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, static_cast(bits(newVal, 43, 0)) << 12); @@ -1609,8 +1615,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_IPAS2E1_Xt: case MISCREG_TLBI_IPAS2LE1_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, static_cast(bits(newVal, 35, 0)) << 12); @@ -1623,8 +1629,8 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) case MISCREG_TLBI_IPAS2E1IS_Xt: case MISCREG_TLBI_IPAS2LE1IS_Xt: { - assert64(tc); - scr = readMiscReg(MISCREG_SCR, tc); + assert64(); + scr = readMiscReg(MISCREG_SCR); TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, static_cast(bits(newVal, 35, 0)) << 12); @@ -2077,18 +2083,17 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) // Generic Timer registers case MISCREG_CNTFRQ ... MISCREG_CNTVOFF: case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2: - getGenericTimer(tc).setMiscReg(misc_reg, newVal); + getGenericTimer().setMiscReg(misc_reg, newVal); break; case MISCREG_ICC_AP0R0 ... MISCREG_ICH_LRC15: case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: - getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); + getGICv3CPUInterface().setMiscReg(misc_reg, newVal); return; case MISCREG_ZCR_EL3: case MISCREG_ZCR_EL2: case MISCREG_ZCR_EL1: - tc->getDecoderPtr()->setSveLen( - (getCurSveVecLenInBits(tc) >> 7) - 1); + tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits() >> 7) - 1); break; } } @@ -2096,7 +2101,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) } BaseISADevice & -ISA::getGenericTimer(ThreadContext *tc) +ISA::getGenericTimer() { // We only need to create an ISA interface the first time we try // to access the timer. @@ -2117,14 +2122,14 @@ ISA::getGenericTimer(ThreadContext *tc) } BaseISADevice & -ISA::getGICv3CPUInterface(ThreadContext *tc) +ISA::getGICv3CPUInterface() { panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); return *gicv3CpuInterface.get(); } unsigned -ISA::getCurSveVecLenInBits(ThreadContext *tc) const +ISA::getCurSveVecLenInBits() const { if (!FullSystem) { return sveVL * 128; diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index b4fbbbfcd..e7c81802d 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -56,7 +56,6 @@ struct ArmISAParams; struct DummyArmISADeviceParams; -class ThreadContext; class Checkpoint; class EventManager; @@ -446,26 +445,17 @@ namespace ArmISA } } - BaseISADevice &getGenericTimer(ThreadContext *tc); - BaseISADevice &getGICv3CPUInterface(ThreadContext *tc); - + BaseISADevice &getGenericTimer(); + BaseISADevice &getGICv3CPUInterface(); private: - inline void assert32(ThreadContext *tc) { - CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc); - assert(cpsr.width); - } - - inline void assert64(ThreadContext *tc) { - CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc); - assert(!cpsr.width); - } + void assert32() { assert(((CPSR)readMiscReg(MISCREG_CPSR)).width); } + void assert64() { assert(!((CPSR)readMiscReg(MISCREG_CPSR)).width); } public: - void clear(ThreadContext *tc); + void clear(); protected: - void clear(); void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst); void clear64(const ArmISAParams *p); void initID32(const ArmISAParams *p); @@ -473,9 +463,9 @@ namespace ArmISA public: RegVal readMiscRegNoEffect(int misc_reg) const; - RegVal readMiscReg(int misc_reg, ThreadContext *tc); + RegVal readMiscReg(int misc_reg); void setMiscRegNoEffect(int misc_reg, RegVal val); - void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc); + void setMiscReg(int misc_reg, RegVal val); RegId flattenRegId(const RegId& regId) const @@ -718,7 +708,7 @@ namespace ArmISA return std::make_pair(lower, upper); } - unsigned getCurSveVecLenInBits(ThreadContext *tc) const; + unsigned getCurSveVecLenInBits() const; unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; } @@ -741,7 +731,9 @@ namespace ArmISA updateRegMap(tmp_cpsr); } - void startup(ThreadContext *tc); + void startup() override; + + void setupThreadContext(); void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) override; @@ -764,9 +756,6 @@ namespace ArmISA return _vecRegRenameMode; } - /// Explicitly import the otherwise hidden startup - using BaseISA::startup; - typedef ArmISAParams Params; const Params *params() const; diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh index d4f6d9f8b..df07763aa 100644 --- a/src/arch/generic/isa.hh +++ b/src/arch/generic/isa.hh @@ -49,10 +49,14 @@ class BaseISA : public SimObject protected: using SimObject::SimObject; + ThreadContext *tc = nullptr; + public: virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {} + + virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; } }; #endif // __ARCH_GENERIC_ISA_HH__ diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index d27f91cb9..616876ceb 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -430,7 +430,7 @@ ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const // Status to TCStatus depending on current thread //template RegVal -ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) +ISA::readMiscReg(int misc_reg, ThreadID tid) { unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); @@ -471,7 +471,7 @@ ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid) // be overwritten. Make sure to handle those particular registers // with care! void -ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) +ISA::setMiscReg(int misc_reg, RegVal val, ThreadID tid) { int reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index 73cb0462a..301f573df 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -72,9 +72,6 @@ namespace MipsISA std::vector bankType; public: - void clear(ThreadContext *tc) { clear(); } - - protected: void clear(); public: @@ -94,15 +91,14 @@ namespace MipsISA RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; //template - RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); + RegVal readMiscReg(int misc_reg, ThreadID tid = 0); RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val); void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0); void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0); //template - void setMiscReg(int misc_reg, RegVal val, - ThreadContext *tc, ThreadID tid=0); + void setMiscReg(int misc_reg, RegVal val, ThreadID tid=0); ////////////////////////////////////////////////////////// // @@ -132,60 +128,20 @@ namespace MipsISA static std::string miscRegNames[NumMiscRegs]; public: - void startup(ThreadContext *tc) {} - - /// Explicitly import the otherwise hidden startup - using BaseISA::startup; - const Params *params() const; ISA(Params *p); RegId flattenRegId(const RegId& regId) const { return regId; } - int - flattenIntIndex(int reg) const - { - return reg; - } - - int - flattenFloatIndex(int reg) const - { - return reg; - } - - int - flattenVecIndex(int reg) const - { - return reg; - } - - int - flattenVecElemIndex(int reg) const - { - return reg; - } - - int - flattenVecPredIndex(int reg) const - { - return reg; - } - + int flattenIntIndex(int reg) const { return reg; } + int flattenFloatIndex(int reg) const { return reg; } + int flattenVecIndex(int reg) const { return reg; } + int flattenVecElemIndex(int reg) const { return reg; } + int flattenVecPredIndex(int reg) const { return reg; } // dummy - int - flattenCCIndex(int reg) const - { - return reg; - } - - int - flattenMiscIndex(int reg) const - { - return reg; - } - + int flattenCCIndex(int reg) const { return reg; } + int flattenMiscIndex(int reg) const { return reg; } }; } diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index c82b7bb41..a0d4a4660 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -54,17 +54,7 @@ class ISA : public BaseISA public: typedef PowerISAParams Params; - void - clear(ThreadContext *tc) - { - clear(); - } - - protected: - void - clear() - { - } + void clear() {} public: RegVal @@ -75,7 +65,7 @@ class ISA : public BaseISA } RegVal - readMiscReg(int misc_reg, ThreadContext *tc) + readMiscReg(int misc_reg) { fatal("Power does not currently have any misc regs defined\n"); return dummy; @@ -88,7 +78,7 @@ class ISA : public BaseISA } void - setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) + setMiscReg(int misc_reg, RegVal val) { fatal("Power does not currently have any misc regs defined\n"); } @@ -138,11 +128,6 @@ class ISA : public BaseISA return reg; } - void startup(ThreadContext *tc) {} - - /// Explicitly import the otherwise hidden startup - using BaseISA::startup; - const Params *params() const; ISA(Params *p); diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index 055c95b35..87c4043a4 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -243,7 +243,7 @@ ISA::readMiscRegNoEffect(int misc_reg) const } RegVal -ISA::readMiscReg(int misc_reg, ThreadContext *tc) +ISA::readMiscReg(int misc_reg) { switch (misc_reg) { case MISCREG_HARTID: @@ -330,7 +330,7 @@ ISA::setMiscRegNoEffect(int misc_reg, RegVal val) } void -ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) +ISA::setMiscReg(int misc_reg, RegVal val) { if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) { // Ignore writes to HPM counters for now diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh index a6c77ce06..1ece3bdf9 100644 --- a/src/arch/riscv/isa.hh +++ b/src/arch/riscv/isa.hh @@ -78,16 +78,13 @@ class ISA : public BaseISA public: typedef RiscvISAParams Params; - void clear(ThreadContext *tc) { clear(); } - - protected: void clear(); public: RegVal readMiscRegNoEffect(int misc_reg) const; - RegVal readMiscReg(int misc_reg, ThreadContext *tc); + RegVal readMiscReg(int misc_reg); void setMiscRegNoEffect(int misc_reg, RegVal val); - void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc); + void setMiscReg(int misc_reg, RegVal val); RegId flattenRegId(const RegId ®Id) const { return regId; } int flattenIntIndex(int reg) const { return reg; } @@ -98,14 +95,9 @@ class ISA : public BaseISA int flattenCCIndex(int reg) const { return reg; } int flattenMiscIndex(int reg) const { return reg; } - void startup(ThreadContext *tc) {} - void serialize(CheckpointOut &cp) const; void unserialize(CheckpointIn &cp); - /// Explicitly import the otherwise hidden startup - using BaseISA::startup; - const Params *params() const; ISA(Params *p); diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 493c5c771..4f2805f32 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -61,10 +61,6 @@ static const PSTATE PstateMask = buildPstateMask(); ISA::ISA(Params *p) : BaseISA(p) { - tickCompare = NULL; - sTickCompare = NULL; - hSTickCompare = NULL; - clear(); } @@ -333,7 +329,7 @@ ISA::readMiscRegNoEffect(int miscReg) const } RegVal -ISA::readMiscReg(int miscReg, ThreadContext * tc) +ISA::readMiscReg(int miscReg) { switch (miscReg) { // tick and stick are aliased to each other in niagra @@ -375,7 +371,7 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc) case MISCREG_QUEUE_NRES_ERROR_HEAD: case MISCREG_QUEUE_NRES_ERROR_TAIL: case MISCREG_HPSTATE: - return readFSReg(miscReg, tc); + return readFSReg(miscReg); } return readMiscRegNoEffect(miscReg); } @@ -562,7 +558,7 @@ ISA::setMiscRegNoEffect(int miscReg, RegVal val) } void -ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) +ISA::setMiscReg(int miscReg, RegVal val) { RegVal new_val = val; @@ -631,7 +627,7 @@ ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) case MISCREG_QUEUE_NRES_ERROR_HEAD: case MISCREG_QUEUE_NRES_ERROR_TAIL: case MISCREG_HPSTATE: - setFSReg(miscReg, val, tc); + setFSReg(miscReg, val); return; } setMiscRegNoEffect(miscReg, new_val); @@ -678,39 +674,18 @@ ISA::serialize(CheckpointOut &cp) const SERIALIZE_SCALAR(res_error_tail); SERIALIZE_SCALAR(nres_error_head); SERIALIZE_SCALAR(nres_error_tail); + Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; - ThreadContext *tc = NULL; - BaseCPU *cpu = NULL; - int tc_num = 0; - bool tick_intr_sched = true; - - if (tickCompare) - tc = tickCompare->getTC(); - else if (sTickCompare) - tc = sTickCompare->getTC(); - else if (hSTickCompare) - tc = hSTickCompare->getTC(); - else - tick_intr_sched = false; - - SERIALIZE_SCALAR(tick_intr_sched); - - if (tc) { - cpu = tc->getCpuPtr(); - tc_num = cpu->findContext(tc); - if (tickCompare && tickCompare->scheduled()) - tick_cmp = tickCompare->when(); - if (sTickCompare && sTickCompare->scheduled()) - stick_cmp = sTickCompare->when(); - if (hSTickCompare && hSTickCompare->scheduled()) - hstick_cmp = hSTickCompare->when(); - - SERIALIZE_OBJPTR(cpu); - SERIALIZE_SCALAR(tc_num); - SERIALIZE_SCALAR(tick_cmp); - SERIALIZE_SCALAR(stick_cmp); - SERIALIZE_SCALAR(hstick_cmp); - } + if (tickCompare && tickCompare->scheduled()) + tick_cmp = tickCompare->when(); + if (sTickCompare && sTickCompare->scheduled()) + stick_cmp = sTickCompare->when(); + if (hSTickCompare && hSTickCompare->scheduled()) + hstick_cmp = hSTickCompare->when(); + + SERIALIZE_SCALAR(tick_cmp); + SERIALIZE_SCALAR(stick_cmp); + SERIALIZE_SCALAR(hstick_cmp); } void @@ -765,35 +740,22 @@ ISA::unserialize(CheckpointIn &cp) UNSERIALIZE_SCALAR(nres_error_tail); Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0; - ThreadContext *tc = NULL; - BaseCPU *cpu = NULL; - int tc_num; - bool tick_intr_sched; - UNSERIALIZE_SCALAR(tick_intr_sched); - if (tick_intr_sched) { - UNSERIALIZE_OBJPTR(cpu); - if (cpu) { - UNSERIALIZE_SCALAR(tc_num); - UNSERIALIZE_SCALAR(tick_cmp); - UNSERIALIZE_SCALAR(stick_cmp); - UNSERIALIZE_SCALAR(hstick_cmp); - tc = cpu->getContext(tc_num); - - if (tick_cmp) { - tickCompare = new TickCompareEvent(this, tc); - schedule(tickCompare, tick_cmp); - } - if (stick_cmp) { - sTickCompare = new STickCompareEvent(this, tc); - schedule(sTickCompare, stick_cmp); - } - if (hstick_cmp) { - hSTickCompare = new HSTickCompareEvent(this, tc); - schedule(hSTickCompare, hstick_cmp); - } - } - } + UNSERIALIZE_SCALAR(tick_cmp); + UNSERIALIZE_SCALAR(stick_cmp); + UNSERIALIZE_SCALAR(hstick_cmp); + if (tick_cmp) { + tickCompare = new TickCompareEvent(this); + schedule(tickCompare, tick_cmp); + } + if (stick_cmp) { + sTickCompare = new STickCompareEvent(this); + schedule(sTickCompare, stick_cmp); + } + if (hstick_cmp) { + hSTickCompare = new HSTickCompareEvent(this); + schedule(hSTickCompare, hstick_cmp); + } } } diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 63eab2e2c..c92855b0b 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -35,7 +35,6 @@ #include "arch/generic/isa.hh" #include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" -#include "cpu/cpuevent.hh" #include "cpu/reg_class.hh" #include "sim/sim_object.hh" @@ -115,29 +114,26 @@ class ISA : public BaseISA // These need to check the int_dis field and if 0 then // set appropriate bit in softint and checkinterrutps on the cpu - void setFSReg(int miscReg, RegVal val, ThreadContext *tc); - RegVal readFSReg(int miscReg, ThreadContext * tc); + void setFSReg(int miscReg, RegVal val); + RegVal readFSReg(int miscReg); // Update interrupt state on softint or pil change - void checkSoftInt(ThreadContext *tc); + void checkSoftInt(); /** Process a tick compare event and generate an interrupt on the cpu if * appropriate. */ - void processTickCompare(ThreadContext *tc); - void processSTickCompare(ThreadContext *tc); - void processHSTickCompare(ThreadContext *tc); + void processTickCompare(); + void processSTickCompare(); + void processHSTickCompare(); - typedef CpuEventWrapper TickCompareEvent; - TickCompareEvent *tickCompare; + typedef EventWrapper TickCompareEvent; + TickCompareEvent *tickCompare = nullptr; - typedef CpuEventWrapper STickCompareEvent; - STickCompareEvent *sTickCompare; + typedef EventWrapper STickCompareEvent; + STickCompareEvent *sTickCompare = nullptr; - typedef CpuEventWrapper HSTickCompareEvent; - HSTickCompareEvent *hSTickCompare; + typedef EventWrapper HSTickCompareEvent; + HSTickCompareEvent *hSTickCompare = nullptr; static const int NumGlobalRegs = 8; static const int NumWindowedRegs = 24; @@ -165,18 +161,12 @@ class ISA : public BaseISA public: - void clear(ThreadContext *tc) { clear(); } + void clear(); void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; - void startup(ThreadContext *tc) {} - - /// Explicitly import the otherwise hidden startup - using BaseISA::startup; - protected: - void clear(); bool isHyperPriv() { return hpstate.hpriv; } bool isPriv() { return hpstate.hpriv || pstate.priv; } bool isNonPriv() { return !isPriv(); } @@ -184,10 +174,10 @@ class ISA : public BaseISA public: RegVal readMiscRegNoEffect(int miscReg) const; - RegVal readMiscReg(int miscReg, ThreadContext *tc); + RegVal readMiscReg(int miscReg); void setMiscRegNoEffect(int miscReg, RegVal val); - void setMiscReg(int miscReg, RegVal val, ThreadContext *tc); + void setMiscReg(int miscReg, RegVal val); RegId flattenRegId(const RegId& regId) const @@ -216,42 +206,14 @@ class ISA : public BaseISA return flatIndex; } - int - flattenFloatIndex(int reg) const - { - return reg; - } - - int - flattenVecIndex(int reg) const - { - return reg; - } - - int - flattenVecElemIndex(int reg) const - { - return reg; - } - - int - flattenVecPredIndex(int reg) const - { - return reg; - } + int flattenFloatIndex(int reg) const { return reg; } + int flattenVecIndex(int reg) const { return reg; } + int flattenVecElemIndex(int reg) const { return reg; } + int flattenVecPredIndex(int reg) const { return reg; } // dummy - int - flattenCCIndex(int reg) const - { - return reg; - } - - int - flattenMiscIndex(int reg) const - { - return reg; - } + int flattenCCIndex(int reg) const { return reg; } + int flattenMiscIndex(int reg) const { return reg; } typedef SparcISAParams Params; diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 3403451b5..1c1dcc2b5 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -44,7 +44,7 @@ using namespace std; void -ISA::checkSoftInt(ThreadContext *tc) +ISA::checkSoftInt() { BaseCPU *cpu = tc->getCpuPtr(); @@ -89,7 +89,7 @@ getMiscRegName(RegIndex index) } void -ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) +ISA::setFSReg(int miscReg, RegVal val) { BaseCPU *cpu = tc->getCpuPtr(); @@ -97,17 +97,17 @@ ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) switch (miscReg) { /* Full system only ASRs */ case MISCREG_SOFTINT: - setMiscRegNoEffect(miscReg, val);; - checkSoftInt(tc); + setMiscRegNoEffect(miscReg, val); + checkSoftInt(); break; case MISCREG_SOFTINT_CLR: - return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); + return setMiscReg(MISCREG_SOFTINT, ~val & softint); case MISCREG_SOFTINT_SET: - return setMiscReg(MISCREG_SOFTINT, val | softint, tc); + return setMiscReg(MISCREG_SOFTINT, val | softint); case MISCREG_TICK_CMPR: if (tickCompare == NULL) - tickCompare = new TickCompareEvent(this, tc); + tickCompare = new TickCompareEvent(this); setMiscRegNoEffect(miscReg, val); if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) cpu->deschedule(tickCompare); @@ -122,7 +122,7 @@ ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) case MISCREG_STICK_CMPR: if (sTickCompare == NULL) - sTickCompare = new STickCompareEvent(this, tc); + sTickCompare = new STickCompareEvent(this); setMiscRegNoEffect(miscReg, val); if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) cpu->deschedule(sTickCompare); @@ -142,7 +142,7 @@ ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) case MISCREG_PIL: setMiscRegNoEffect(miscReg, val); - checkSoftInt(tc); + checkSoftInt(); break; case MISCREG_HVER: @@ -193,7 +193,7 @@ ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) case MISCREG_HSTICK_CMPR: if (hSTickCompare == NULL) - hSTickCompare = new HSTickCompareEvent(this, tc); + hSTickCompare = new HSTickCompareEvent(this); setMiscRegNoEffect(miscReg, val); if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) cpu->deschedule(hSTickCompare); @@ -244,7 +244,7 @@ ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) } RegVal -ISA::readFSReg(int miscReg, ThreadContext * tc) +ISA::readFSReg(int miscReg) { uint64_t temp; @@ -318,13 +318,13 @@ ISA::readFSReg(int miscReg, ThreadContext * tc) } void -ISA::processTickCompare(ThreadContext *tc) +ISA::processTickCompare() { panic("tick compare not implemented\n"); } void -ISA::processSTickCompare(ThreadContext *tc) +ISA::processSTickCompare() { BaseCPU *cpu = tc->getCpuPtr(); @@ -340,7 +340,7 @@ ISA::processSTickCompare(ThreadContext *tc) DPRINTF(Timer, "STick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { - setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); + setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16)); } } else { cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay))); @@ -348,7 +348,7 @@ ISA::processSTickCompare(ThreadContext *tc) } void -ISA::processHSTickCompare(ThreadContext *tc) +ISA::processHSTickCompare() { BaseCPU *cpu = tc->getCpuPtr(); @@ -367,7 +367,7 @@ ISA::processHSTickCompare(ThreadContext *tc) DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { - setMiscReg(MISCREG_HINTP, 1, tc); + setMiscReg(MISCREG_HINTP, 1); } // Need to do something to cause interrupt to happen here !!! @todo } else { diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 874d75b02..a142bcf71 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -40,8 +40,7 @@ namespace X86ISA void ISA::updateHandyM5Reg(Efer efer, CR0 cr0, - SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, - ThreadContext *tc) + SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) { HandyM5Reg m5reg = 0; if (efer.lma) { @@ -154,7 +153,7 @@ ISA::readMiscRegNoEffect(int miscReg) const } RegVal -ISA::readMiscReg(int miscReg, ThreadContext * tc) +ISA::readMiscReg(int miscReg) { if (miscReg == MISCREG_TSC) { return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); @@ -218,7 +217,7 @@ ISA::setMiscRegNoEffect(int miscReg, RegVal val) } void -ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) +ISA::setMiscReg(int miscReg, RegVal val) { RegVal newVal = val; switch(miscReg) @@ -250,8 +249,7 @@ ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) newCR0, regVal[MISCREG_CS_ATTR], regVal[MISCREG_SS_ATTR], - regVal[MISCREG_RFLAGS], - tc); + regVal[MISCREG_RFLAGS]); } break; case MISCREG_CR2: @@ -292,8 +290,7 @@ ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) regVal[MISCREG_CR0], newCSAttr, regVal[MISCREG_SS_ATTR], - regVal[MISCREG_RFLAGS], - tc); + regVal[MISCREG_RFLAGS]); } break; case MISCREG_SS_ATTR: @@ -301,8 +298,7 @@ ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) regVal[MISCREG_CR0], regVal[MISCREG_CS_ATTR], val, - regVal[MISCREG_RFLAGS], - tc); + regVal[MISCREG_RFLAGS]); break; // These segments always actually use their bases, or in other words // their effective bases must stay equal to their actual bases. @@ -409,8 +405,7 @@ ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) regVal[MISCREG_CR0], regVal[MISCREG_CS_ATTR], regVal[MISCREG_SS_ATTR], - regVal[MISCREG_RFLAGS], - tc); + regVal[MISCREG_RFLAGS]); return; default: break; @@ -432,13 +427,13 @@ ISA::unserialize(CheckpointIn &cp) regVal[MISCREG_CR0], regVal[MISCREG_CS_ATTR], regVal[MISCREG_SS_ATTR], - regVal[MISCREG_RFLAGS], - NULL); + regVal[MISCREG_RFLAGS]); } void -ISA::startup(ThreadContext *tc) +ISA::setThreadContext(ThreadContext *_tc) { + BaseISA::setThreadContext(_tc); tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]); } diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 774321ac3..855c8e7b3 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -52,23 +52,21 @@ namespace X86ISA protected: RegVal regVal[NUM_MISCREGS]; void updateHandyM5Reg(Efer efer, CR0 cr0, - SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, - ThreadContext *tc); - void clear(); + SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags); public: - typedef X86ISAParams Params; + void clear(); - void clear(ThreadContext *tc) { clear(); } + typedef X86ISAParams Params; ISA(Params *p); const Params *params() const; RegVal readMiscRegNoEffect(int miscReg) const; - RegVal readMiscReg(int miscReg, ThreadContext *tc); + RegVal readMiscReg(int miscReg); void setMiscRegNoEffect(int miscReg, RegVal val); - void setMiscReg(int miscReg, RegVal val, ThreadContext *tc); + void setMiscReg(int miscReg, RegVal val); RegId flattenRegId(const RegId& regId) const @@ -88,11 +86,7 @@ namespace X86ISA return regId; } - int - flattenIntIndex(int reg) const - { - return reg & ~IntFoldBit; - } + int flattenIntIndex(int reg) const { return reg & ~IntFoldBit; } int flattenFloatIndex(int reg) const @@ -104,44 +98,16 @@ namespace X86ISA return reg; } - int - flattenVecIndex(int reg) const - { - return reg; - } - - int - flattenVecElemIndex(int reg) const - { - return reg; - } - - int - flattenVecPredIndex(int reg) const - { - return reg; - } - - int - flattenCCIndex(int reg) const - { - return reg; - } - - int - flattenMiscIndex(int reg) const - { - return reg; - } + int flattenVecIndex(int reg) const { return reg; } + int flattenVecElemIndex(int reg) const { return reg; } + int flattenVecPredIndex(int reg) const { return reg; } + int flattenCCIndex(int reg) const { return reg; } + int flattenMiscIndex(int reg) const { return reg; } void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; - void startup(ThreadContext *tc); - - /// Explicitly import the otherwise hidden startup - using BaseISA::startup; - + void setThreadContext(ThreadContext *_tc) override; }; } diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 6260bd9ef..f1dc6bded 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -89,7 +89,6 @@ SimObject('TimingExpr.py') Source('activity.cc') Source('base.cc') -Source('cpuevent.cc') Source('exetrace.cc') Source('exec_context.cc') Source('func_unit.cc') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 2e8d73871..c90314565 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -54,7 +54,6 @@ #include "base/output.hh" #include "base/trace.hh" #include "cpu/checker/cpu.hh" -#include "cpu/cpuevent.hh" #include "cpu/profile.hh" #include "cpu/thread_context.hh" #include "debug/Mwait.hh" @@ -440,6 +439,7 @@ BaseCPU::registerThreadContexts() tc->getProcessPtr()->assignThreadContext(tc->contextId()); interrupts[tid]->setThreadContext(tc); + tc->getIsaPtr()->setThreadContext(tc); } } @@ -569,9 +569,9 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) ThreadContext *newTC = threadContexts[i]; ThreadContext *oldTC = oldCPU->threadContexts[i]; - newTC->takeOverFrom(oldTC); + newTC->getIsaPtr()->setThreadContext(newTC); - CpuEvent::replaceThreadContext(oldTC, newTC); + newTC->takeOverFrom(oldTC); assert(newTC->contextId() == oldTC->contextId()); assert(newTC->threadId() == oldTC->threadId()); diff --git a/src/cpu/cpuevent.cc b/src/cpu/cpuevent.cc deleted file mode 100644 index 13b4f6809..000000000 --- a/src/cpu/cpuevent.cc +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "cpu/cpuevent.hh" - -/** Static list of all CpuEvent objects so we can modify their thread - * contexts as needed. */ -CpuEvent::CpuEventList CpuEvent::cpuEventList; - -CpuEvent::~CpuEvent() -{ - CpuEventList::iterator i; - - // delete the event from the global list - for (i = cpuEventList.begin(); i != cpuEventList.end(); ) { - if (*i == this) - i = cpuEventList.erase(i); - else - i++; - } -} - -void -CpuEvent::replaceThreadContext(ThreadContext *oldTc, ThreadContext *newTc) -{ - CpuEventList::iterator i; - - // Update any events that have the old thread context with the new thread - // context - for (i = cpuEventList.begin(); i != cpuEventList.end(); i++) { - if ((*i)->tc == oldTc) - (*i)->tc = newTc; - } -} diff --git a/src/cpu/cpuevent.hh b/src/cpu/cpuevent.hh deleted file mode 100644 index 9da2ddd96..000000000 --- a/src/cpu/cpuevent.hh +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __CPU_CPUEVENT_HH__ -#define __CPU_CPUEVENT_HH__ - -#include - -#include "sim/eventq.hh" - -class ThreadContext; - -/** - * This class creates a global list of events that need a pointer to a - * thread context. When a switchover takes place the events can be - * migrated to the new thread context, otherwise you could have a wake - * timer interrupt go off on a switched out cpu or other unfortunate - * events. This object MUST be dynamically allocated to avoid it being - * deleted after a cpu switch happens. - */ -class CpuEvent : public Event -{ - protected: - /** type of global list of cpu events. */ - typedef std::vector CpuEventList; - - /** Static list of cpu events that is searched every time a cpu switch - * happens. */ - static CpuEventList cpuEventList; - - /** The thread context that is switched to the new cpus. */ - ThreadContext *tc; - - public: - CpuEvent(ThreadContext *_tc, Priority p = Default_Pri) - : Event(p), tc(_tc) - { cpuEventList.push_back(this); } - - /** delete the cpu event from the global list. */ - ~CpuEvent(); - - /** Update all events switching old tc to new tc. - * @param oldTc the old thread context we are switching from - * @param newTc the new thread context we are switching to. - */ - static void replaceThreadContext(ThreadContext *oldTc, - ThreadContext *newTc); - ThreadContext* getTC() { return tc; } -}; - -template -class CpuEventWrapper : public CpuEvent -{ - private: - T *object; - - public: - CpuEventWrapper(T *obj, ThreadContext *_tc, Priority p = Default_Pri) - : CpuEvent(_tc, p), object(obj) - { } - void process() { (object->*F)(tc); } -}; - -#endif // __CPU_CPUEVENT_HH__ - diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc index d44bb3d23..18aead84e 100644 --- a/src/cpu/kvm/base.cc +++ b/src/cpu/kvm/base.cc @@ -155,8 +155,6 @@ BaseKvmCPU::startup() inform("KVM: Coalesced not supported by host OS\n"); } - thread->startup(); - Event *startupEvent( new EventFunctionWrapper([this]{ startupThread(); }, name(), true)); schedule(startupEvent, curTick()); diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc index e0ebef61f..a375e07be 100644 --- a/src/cpu/minor/cpu.cc +++ b/src/cpu/minor/cpu.cc @@ -161,10 +161,8 @@ MinorCPU::startup() BaseCPU::startup(); - for (ThreadID tid = 0; tid < numThreads; tid++) { - threads[tid]->startup(); + for (ThreadID tid = 0; tid < numThreads; tid++) pipeline->wakeupFetch(tid); - } } DrainState diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index befd162fb..b3faf315d 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -599,8 +599,6 @@ void FullO3CPU::startup() { BaseCPU::startup(); - for (int tid = 0; tid < numThreads; ++tid) - isa[tid]->startup(threadContexts[tid]); fetch.startupStage(); decode.startupStage(); @@ -1180,7 +1178,7 @@ RegVal FullO3CPU::readMiscReg(int misc_reg, ThreadID tid) { miscRegfileReads++; - return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); + return this->isa[tid]->readMiscReg(misc_reg); } template @@ -1195,7 +1193,7 @@ void FullO3CPU::setMiscReg(int misc_reg, RegVal val, ThreadID tid) { miscRegfileWrites++; - this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); + this->isa[tid]->setMiscReg(misc_reg, val); } template diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 7a2c83070..d02be717b 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -200,7 +200,7 @@ template void O3ThreadContext::clearArchRegs() { - cpu->isa[thread->threadId()]->clear(this); + cpu->isa[thread->threadId()]->clear(); } template diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 2a7b00aca..c6d57616b 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -685,11 +685,3 @@ BaseSimpleCPU::advancePC(const Fault &fault) } } } - -void -BaseSimpleCPU::startup() -{ - BaseCPU::startup(); - for (auto& t_info : threadInfo) - t_info->thread->startup(); -} diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index df17c2672..323850ac5 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -133,8 +133,6 @@ class BaseSimpleCPU : public BaseCPU void regStats() override; void resetStats() override; - void startup() override; - virtual Fault readMem(Addr addr, uint8_t* data, unsigned size, Request::Flags flags, const std::vector& byte_enable = diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index ef8e074e0..d0c6bf440 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -156,12 +156,6 @@ SimpleThread::unserialize(CheckpointIn &cp) ::unserialize(*this, cp); } -void -SimpleThread::startup() -{ - isa->startup(this); -} - void SimpleThread::dumpFuncProfile() { diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index d63bf0bf9..6118541f2 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -158,7 +158,6 @@ class SimpleThread : public ThreadState, public ThreadContext void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; - void startup(); /*************************************************************** * SimpleThread functions to provide CPU with access to various @@ -296,7 +295,7 @@ class SimpleThread : public ThreadState, public ThreadContext for (auto &pred_reg: vecPredRegs) pred_reg.reset(); ccRegs.fill(0); - isa->clear(this); + isa->clear(); } // @@ -558,7 +557,7 @@ class SimpleThread : public ThreadState, public ThreadContext RegVal readMiscReg(RegIndex misc_reg) override { - return isa->readMiscReg(misc_reg, this); + return isa->readMiscReg(misc_reg); } void @@ -570,7 +569,7 @@ class SimpleThread : public ThreadState, public ThreadContext void setMiscReg(RegIndex misc_reg, RegVal val) override { - return isa->setMiscReg(misc_reg, val, this); + return isa->setMiscReg(misc_reg, val); } RegId -- 2.30.2