From 262a3ae1adedf6e2c2389b484a01cbf0ddea3a72 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 10 Jul 2021 17:24:10 +0100 Subject: [PATCH] whoops forgot elif in SVP64Asm translation, detection of ffmadds overwritten --- src/openpower/sv/trans/svp64.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 05f97632..6fc57705 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -818,7 +818,7 @@ class SVP64Asm: opcode |= 1 # Rc, bit 31. yield ".long 0x%x" % opcode # argh, sv.ffadds etc. need to be done manually - if v30b_op == 'ffadds': + elif v30b_op == 'ffadds': opcode = 59 << (32-6) # bits 0..6 (MSB0) opcode |= int(v30b_newfields[0]) << (32-11) # FRT opcode |= int(v30b_newfields[1]) << (32-16) # FRA -- 2.30.2