From 26391cceaa17d9452f9adcf321aa05731eb50a39 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 18 Apr 2019 17:48:15 -0700 Subject: [PATCH] intel/compiler: Lower ffma on Gen4 and Gen5 flrp32 is also a 3-source instruction, but there is another pending series that handles that for Gen4 and Gen5. v2: Rebase on "intel/compiler: Don't have sepearate, per-Gen nir_options" Reviewed-by: Jason Ekstrand Reviewed-by: Matt Turner --- src/intel/compiler/brw_compiler.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index f1acf838887..44296083711 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -183,6 +183,10 @@ brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo) nir_options->lower_flrp32 = true; } } + + /* Prior to Gen6, there are no three source operations. */ + nir_options->lower_ffma = devinfo->gen < 6; + nir_options->lower_int64_options = int64_options; nir_options->lower_doubles_options = fp64_options; compiler->glsl_compiler_options[i].NirOptions = nir_options; -- 2.30.2