From 263f5a2cf97e455e48dbd7728cb0ac10fd699746 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Thu, 10 Sep 2015 18:27:53 +0200 Subject: [PATCH] radeonsi: skip drawing if GS ring allocations fail MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Cc: 11.0 Acked-by: Christian König Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/si_state_shaders.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 11b58e8b3ca..bc7fdb3e94a 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1069,9 +1069,15 @@ static void si_init_gs_rings(struct si_context *sctx) sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT, esgs_ring_size); + if (!sctx->esgs_ring) + return; sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT, gsvs_ring_size); + if (!sctx->gsvs_ring) { + pipe_resource_reference(&sctx->esgs_ring, NULL); + return; + } /* Append these registers to the init config state. */ if (sctx->b.chip_class >= CIK) { @@ -1443,8 +1449,11 @@ bool si_update_shaders(struct si_context *sctx) si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4); si_update_so(sctx, sctx->gs_shader); - if (!sctx->gsvs_ring) + if (!sctx->gsvs_ring) { si_init_gs_rings(sctx); + if (!sctx->gsvs_ring) + return false; + } si_update_gs_rings(sctx); } else { -- 2.30.2