From 263fc47728977f5ebd8efe265ee2d61fb0edcc18 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 29 Mar 2015 12:16:33 +0200 Subject: [PATCH] platforms/kc705: fix .bin generation with ISE and Vivado --- mibuild/platforms/kc705.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index b2df99d0..c1db69a8 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -383,7 +383,11 @@ class Platform(XilinxPlatform): def __init__(self, toolchain="vivado", programmer="xc3sprog"): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain=toolchain) - self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" + if toolchain == "ise": + self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" + elif toolchain == "vivado": + self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] + self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.programmer = programmer def create_programmer(self): -- 2.30.2