From 2641a9b24f176ca3edf83c471276fdc8f1d0ea86 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Tue, 31 May 2011 14:51:38 -0700
Subject: [PATCH] [sim] minor sim cleanup

---
 riscv/mmu.h        | 22 ++++++----------------
 riscv/processor.cc |  4 ++--
 2 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/riscv/mmu.h b/riscv/mmu.h
index b107b71..21b493e 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -48,7 +48,8 @@ public:
 
   #define load_func(type) \
     type##_t load_##type(reg_t addr) { \
-      check_align(addr, sizeof(type##_t), false, false); \
+      if(unlikely(addr % sizeof(type##_t))) \
+        throw trap_load_address_misaligned; \
       addr = translate(addr, false, false); \
       dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), false); \
       return *(type##_t*)(mem+addr); \
@@ -56,7 +57,8 @@ public:
 
   #define store_func(type) \
     void store_##type(reg_t addr, type##_t val) { \
-      check_align(addr, sizeof(type##_t), true, false); \
+      if(unlikely(addr % sizeof(type##_t))) \
+        throw trap_store_address_misaligned; \
       addr = translate(addr, true, false); \
       dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), true); \
       *(type##_t*)(mem+addr) = val; \
@@ -86,7 +88,8 @@ public:
     else
     #endif
     {
-      check_align(addr, 4, false, true);
+      if(unlikely(addr % 4))
+        throw trap_instruction_address_misaligned;
       reg_t paddr = translate(addr, false, true);
       insn = *(insn_t*)(mem+paddr);
 
@@ -156,19 +159,6 @@ private:
   icsim_t* itlbsim;
   icsim_t* dtlbsim;
 
-  void check_align(reg_t addr, int size, bool store, bool fetch)
-  {
-    if(unlikely(addr & (size-1)))
-    {
-      badvaddr = addr;
-      if(fetch)
-        throw trap_instruction_address_misaligned;
-      if(store)
-        throw trap_store_address_misaligned;
-      throw trap_load_address_misaligned;
-    }
-  }
-
   reg_t translate(reg_t addr, bool store, bool fetch)
   {
     reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
diff --git a/riscv/processor.cc b/riscv/processor.cc
index e22030b..eea2ce2 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -184,7 +184,7 @@ void processor_t::step(size_t n, bool noisy)
       execute_insn(true);
     else 
     {
-      for( ; i < n-3; i+=4)
+      for( ; n > 3 && i < n-3; i+=4)
       {
         execute_insn(false);
         execute_insn(false);
@@ -195,7 +195,7 @@ void processor_t::step(size_t n, bool noisy)
         execute_insn(false);
     }
 
-    return;
+    break;
   }
   catch(trap_t t)
   {
-- 
2.30.2