From 26558305c986c30f6f786e77769c566c6104f085 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Tue, 17 May 2022 22:25:45 -0700 Subject: [PATCH] add another grevlut form based on what I proposed adds xor gates at input/output and has the immediate luts go to alternating halves -- still is built on just a layer of aoi, no extra muxes needed in grev matrix. --- openpower/sv/grevlut_grev_gorc.py | 63 +++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 openpower/sv/grevlut_grev_gorc.py diff --git a/openpower/sv/grevlut_grev_gorc.py b/openpower/sv/grevlut_grev_gorc.py new file mode 100644 index 000000000..329da7784 --- /dev/null +++ b/openpower/sv/grevlut_grev_gorc.py @@ -0,0 +1,63 @@ +def aoi(a, b, c, d): + return ~((a & b) | (c & d)) + + +def oai(a, b, c, d): + return ~((a | b) & (c | d)) + + +def and_or(a, b, c, d): + return ((a & b) | (c & d)) + + +def grev_wires(a, step): + retval = 0 + for i in range(64): + if a & (1 << i): + retval |= 1 << (i ^ step) + return retval + + +def grev_mask(step): + retval = 0 + for i in range(64): + if ~i & step: + retval |= 1 << i + return retval + + +def grevlut_grev_gorc(a, sh, imm_lut, inv_in, inv_out): + if inv_in: + a = ~a + for log2_step in range(6): + step = 2 ** log2_step + grev_mask_v = grev_mask(step) + sh_bit = (sh >> log2_step) & 1 + b = d = 0 + if (imm_lut >> sh_bit) & 0x1: + b |= grev_mask_v + if (imm_lut >> sh_bit) & 0x4: + b |= ~grev_mask_v + if (imm_lut >> sh_bit) & 0x10: + d |= grev_mask_v + if (imm_lut >> sh_bit) & 0x40: + d |= ~grev_mask_v + c = grev_wires(a, 2 ** log2_step) + if log2_step % 2 != 0: + a = oai(a, ~b, c, ~d) + else: + a = aoi(a, b, c, d) + if inv_out: + a = ~a + a %= 2**64 + return a + + +def case(a, sh, imm_lut, inv_in, inv_out): + v = grevlut_grev_gorc(a, sh, imm_lut, inv_in, inv_out) + print(f"grevlut_grev_gorc({hex(a)}, {hex(sh)}, {bin(imm_lut)}, " + f"{inv_in}, {inv_out}) = {hex(v)}") + + +for i in range(64): + case(0x5555_5555_5555_5555, i, 0b1010010, True, False) -- 2.30.2