From 2664351dfeeba2c1d0de272cdf6d5fd940a367e9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 23 Oct 2016 21:28:29 +0200 Subject: [PATCH] gallium/radeon: re-order radeon_surf::dcc and htile members MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle --- src/gallium/drivers/radeon/radeon_winsys.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index cec1274abee..2330cddf631 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -298,7 +298,12 @@ struct radeon_surf { * changed by the calculator. */ uint64_t surf_size; + uint64_t dcc_size; + uint64_t htile_size; + uint32_t surf_alignment; + uint32_t dcc_alignment; + uint32_t htile_alignment; /* This applies to EG and later. */ unsigned bankw:4; /* max 8 */ @@ -323,11 +328,6 @@ struct radeon_surf { struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; - - uint64_t dcc_size; - uint32_t dcc_alignment; - uint64_t htile_size; - uint32_t htile_alignment; }; struct radeon_bo_list_item { -- 2.30.2