From 26869fdb471ee8d0fcdcf3d27f5ac5dbadc7b5e0 Mon Sep 17 00:00:00 2001 From: Pat Haugen Date: Tue, 24 May 2016 22:24:16 +0000 Subject: [PATCH] lhs-1.c: Fix testcase to avoid subreg changes. * gcc.target/powerpc/lhs-1.c: Fix testcase to avoid subreg changes. From-SVN: r236672 --- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/lhs-1.c | 19 ++++++------------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 39c6b27cebf..a2821a7c9c7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-05-24 Pat Haugen + + PR target/71050 + * gcc.target/powerpc/lhs-1.c: Fix testcase to avoid subreg changes. + 2016-05-24 Paolo Carlini PR c++/50436 diff --git a/gcc/testsuite/gcc.target/powerpc/lhs-1.c b/gcc/testsuite/gcc.target/powerpc/lhs-1.c index 4bd8c890b95..2979711e392 100644 --- a/gcc/testsuite/gcc.target/powerpc/lhs-1.c +++ b/gcc/testsuite/gcc.target/powerpc/lhs-1.c @@ -4,19 +4,12 @@ /* { dg-options "-O2 -mcpu=power5" } */ /* { dg-final { scan-assembler-times "nop" 3 } } */ -/* Test generation of nops in load hit store situation. */ +/* Test generation of nops in load hit store situation. Make sure enough nop + insns are generated to move the load to a new dispatch group. With the + simple stw/lwz pair below, that would be 3 nop insns for Power5. */ -typedef union { - double val; - struct { - unsigned int w1; - unsigned int w2; - }; -} words; - -unsigned int f (double d, words *u) +unsigned int f (volatile unsigned int *u, unsigned int u2) { - u->val = d; - return u->w2; + *u = u2; + return *u; } - -- 2.30.2