From 26a4d424e19c57db7055f134eff87f26fa61cae5 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Thu, 11 Dec 2014 13:34:22 +0000 Subject: [PATCH] [ARM] Fix names of some rounding intrinsics, impement vrndx_f32 and vrndxq_f32 * config/arm/arm_neon.h (vrndqn_f32): Rename to... (vrndnq_f32): ... this. (vrndqa_f32): Rename to... (vrndaq_f32): ... this. (vrndqp_f32): Rename to... (vrndpq_f32): ... this. (vrndqm_f32): Rename to... (vrndmq_f32): ... this. (vrndx_f32): New intrinsic. (vrndxq_f32): Likewise. * config/arm/arm_neon.h (vrndqn_f32): Rename to... (vrndnq_f32): ... this. (vrndqa_f32): Rename to... (vrndaq_f32): ... this. (vrndqp_f32): Rename to... (vrndpq_f32): ... this. (vrndqm_f32): Rename to... (vrndmq_f32): ... this. (vrndx_f32): New intrinsic. (vrndxq_f32): Likewise. From-SVN: r218622 --- gcc/ChangeLog | 13 +++++++++ gcc/config/arm/arm_neon.h | 27 ++++++++++++++++--- gcc/testsuite/ChangeLog | 13 +++++++++ .../arm/neon/{vrndqaf32.c => vrndaqf32.c} | 6 ++--- .../arm/neon/{vrndqmf32.c => vrndmqf32.c} | 6 ++--- .../arm/neon/{vrndqnf32.c => vrndnqf32.c} | 6 ++--- .../arm/neon/{vrndqpf32.c => vrndpqf32.c} | 6 ++--- .../gcc.target/arm/simd/neon-vrndx_f32_1.c | 17 ++++++++++++ .../gcc.target/arm/simd/neon-vrndxq_f32_1.c | 17 ++++++++++++ 9 files changed, 95 insertions(+), 16 deletions(-) rename gcc/testsuite/gcc.target/arm/neon/{vrndqaf32.c => vrndaqf32.c} (78%) rename gcc/testsuite/gcc.target/arm/neon/{vrndqmf32.c => vrndmqf32.c} (78%) rename gcc/testsuite/gcc.target/arm/neon/{vrndqnf32.c => vrndnqf32.c} (78%) rename gcc/testsuite/gcc.target/arm/neon/{vrndqpf32.c => vrndpqf32.c} (78%) create mode 100644 gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 24bd895d002..530147080b9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2014-12-11 Kyrylo Tkachov + + * config/arm/arm_neon.h (vrndqn_f32): Rename to... + (vrndnq_f32): ... this. + (vrndqa_f32): Rename to... + (vrndaq_f32): ... this. + (vrndqp_f32): Rename to... + (vrndpq_f32): ... this. + (vrndqm_f32): Rename to... + (vrndmq_f32): ... this. + (vrndx_f32): New intrinsic. + (vrndxq_f32): Likewise. + 2014-12-11 Marek Polacek * fold-const.c (fold_negate_expr): Add ANY_INTEGRAL_TYPE_P check. diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index e58b772ee29..377f8731ac6 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -1471,7 +1471,7 @@ vrndn_f32 (float32x2_t __a) #endif #if __ARM_ARCH >= 8 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrndqn_f32 (float32x4_t __a) +vrndnq_f32 (float32x4_t __a) { return (float32x4_t)__builtin_neon_vrintnv4sf (__a); } @@ -1487,7 +1487,7 @@ vrnda_f32 (float32x2_t __a) #endif #if __ARM_ARCH >= 8 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrndqa_f32 (float32x4_t __a) +vrndaq_f32 (float32x4_t __a) { return (float32x4_t)__builtin_neon_vrintav4sf (__a); } @@ -1503,7 +1503,7 @@ vrndp_f32 (float32x2_t __a) #endif #if __ARM_ARCH >= 8 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrndqp_f32 (float32x4_t __a) +vrndpq_f32 (float32x4_t __a) { return (float32x4_t)__builtin_neon_vrintpv4sf (__a); } @@ -1519,12 +1519,31 @@ vrndm_f32 (float32x2_t __a) #endif #if __ARM_ARCH >= 8 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vrndqm_f32 (float32x4_t __a) +vrndmq_f32 (float32x4_t __a) { return (float32x4_t)__builtin_neon_vrintmv4sf (__a); } #endif + +#if __ARM_ARCH >= 8 +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vrndx_f32 (float32x2_t __a) +{ + return (float32x2_t)__builtin_neon_vrintxv2sf (__a); +} + +#endif + +#if __ARM_ARCH >= 8 +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vrndxq_f32 (float32x4_t __a) +{ + return (float32x4_t)__builtin_neon_vrintxv4sf (__a); +} + +#endif + #if __ARM_ARCH >= 8 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) vrnd_f32 (float32x2_t __a) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index aab05553f06..0ab4b39befe 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2014-12-11 Kyrylo Tkachov + + * config/arm/arm_neon.h (vrndqn_f32): Rename to... + (vrndnq_f32): ... this. + (vrndqa_f32): Rename to... + (vrndaq_f32): ... this. + (vrndqp_f32): Rename to... + (vrndpq_f32): ... this. + (vrndqm_f32): Rename to... + (vrndmq_f32): ... this. + (vrndx_f32): New intrinsic. + (vrndxq_f32): Likewise. + 2014-12-11 Kyrylo Tkachov kyrylo.tkachov@arm.com * lib/target-utils.exp: New file. diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c similarity index 78% rename from gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c rename to gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c index b7b5d73c485..c1acb64e8e7 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqaf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vrndaqf32.c @@ -1,4 +1,4 @@ -/* Test the `vrndqaf32' ARM Neon intrinsic. */ +/* Test the `vrndaq_f32' ARM Neon intrinsic. */ /* This file was autogenerated by neon-testgen. */ /* { dg-do assemble } */ @@ -8,12 +8,12 @@ #include "arm_neon.h" -void test_vrndqaf32 (void) +void test_vrndaqf32 (void) { float32x4_t out_float32x4_t; float32x4_t arg0_float32x4_t; - out_float32x4_t = vrndqa_f32 (arg0_float32x4_t); + out_float32x4_t = vrndaq_f32 (arg0_float32x4_t); } /* { dg-final { scan-assembler "vrinta\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c similarity index 78% rename from gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c rename to gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c index 6d16bfc9334..306d4f8b03b 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqmf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vrndmqf32.c @@ -1,4 +1,4 @@ -/* Test the `vrndqmf32' ARM Neon intrinsic. */ +/* Test the `vrndmq_f32' ARM Neon intrinsic. */ /* This file was autogenerated by neon-testgen. */ /* { dg-do assemble } */ @@ -8,12 +8,12 @@ #include "arm_neon.h" -void test_vrndqmf32 (void) +void test_vrndmqf32 (void) { float32x4_t out_float32x4_t; float32x4_t arg0_float32x4_t; - out_float32x4_t = vrndqm_f32 (arg0_float32x4_t); + out_float32x4_t = vrndmq_f32 (arg0_float32x4_t); } /* { dg-final { scan-assembler "vrintm\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c similarity index 78% rename from gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c rename to gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c index b31ca95db42..0a70529bd66 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqnf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vrndnqf32.c @@ -1,4 +1,4 @@ -/* Test the `vrndqnf32' ARM Neon intrinsic. */ +/* Test the `vrndnq_f32' ARM Neon intrinsic. */ /* This file was autogenerated by neon-testgen. */ /* { dg-do assemble } */ @@ -8,12 +8,12 @@ #include "arm_neon.h" -void test_vrndqnf32 (void) +void test_vrndnqf32 (void) { float32x4_t out_float32x4_t; float32x4_t arg0_float32x4_t; - out_float32x4_t = vrndqn_f32 (arg0_float32x4_t); + out_float32x4_t = vrndnq_f32 (arg0_float32x4_t); } /* { dg-final { scan-assembler "vrintn\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c b/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c similarity index 78% rename from gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c rename to gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c index 5c4a8669069..723fee4e576 100644 --- a/gcc/testsuite/gcc.target/arm/neon/vrndqpf32.c +++ b/gcc/testsuite/gcc.target/arm/neon/vrndpqf32.c @@ -1,4 +1,4 @@ -/* Test the `vrndqpf32' ARM Neon intrinsic. */ +/* Test the `vrndpq_f32' ARM Neon intrinsic. */ /* This file was autogenerated by neon-testgen. */ /* { dg-do assemble } */ @@ -8,12 +8,12 @@ #include "arm_neon.h" -void test_vrndqpf32 (void) +void test_vrndpqf32 (void) { float32x4_t out_float32x4_t; float32x4_t arg0_float32x4_t; - out_float32x4_t = vrndqp_f32 (arg0_float32x4_t); + out_float32x4_t = vrndpq_f32 (arg0_float32x4_t); } /* { dg-final { scan-assembler "vrintp\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c b/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c new file mode 100644 index 00000000000..3d2f27fa666 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/neon-vrndx_f32_1.c @@ -0,0 +1,17 @@ +/* Test the `vrndx_f32' ARM Neon intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +float32x2_t +test_vrndx_f32 (float32x2_t in) +{ + return vrndx_f32 (in); +} + +/* { dg-final { scan-assembler "vrintx\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c b/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c new file mode 100644 index 00000000000..c89cb248284 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/neon-vrndxq_f32_1.c @@ -0,0 +1,17 @@ +/* Test the `vrndxq_f32' ARM Neon intrinsic. */ + +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_neon } */ + +#include "arm_neon.h" + +float32x4_t +test_vrndxq_f32 (float32x4_t in) +{ + return vrndxq_f32 (in); +} + +/* { dg-final { scan-assembler "vrintx\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+\n" } } */ +/* { dg-final { cleanup-saved-temps } } */ -- 2.30.2