From 26d7f0f08e861335dc7bb2b51759c2206915a25a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 8 Sep 2015 15:05:31 -0700 Subject: [PATCH] Add facility to instrument specific opcodes It's not ideal, because it requires modifying tracer.h. A more general facility would allow overriding the instruction execution function for a given opcode dynamically. --- riscv/insn_template.cc | 2 ++ riscv/insn_template.h | 1 + riscv/tracer.h | 11 +++++++++++ 3 files changed, 14 insertions(+) create mode 100644 riscv/tracer.h diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc index 35f67a0..1e79326 100644 --- a/riscv/insn_template.cc +++ b/riscv/insn_template.cc @@ -7,6 +7,7 @@ reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc) int xlen = 32; reg_t npc = sext_xlen(pc + insn_length(OPCODE)); #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); return npc; } @@ -15,5 +16,6 @@ reg_t rv64_NAME(processor_t* p, insn_t insn, reg_t pc) int xlen = 64; reg_t npc = sext_xlen(pc + insn_length(OPCODE)); #include "insns/NAME.h" + trace_opcode(p, OPCODE, insn); return npc; } diff --git a/riscv/insn_template.h b/riscv/insn_template.h index 1a0fd2e..f632872 100644 --- a/riscv/insn_template.h +++ b/riscv/insn_template.h @@ -3,6 +3,7 @@ #include "mmu.h" #include "mulhi.h" #include "softfloat.h" +#include "tracer.h" #include "platform.h" // softfloat isNaNF32UI, etc. #include "internals.h" // ditto #include diff --git a/riscv/tracer.h b/riscv/tracer.h new file mode 100644 index 0000000..9f1bc78 --- /dev/null +++ b/riscv/tracer.h @@ -0,0 +1,11 @@ +// See LICENSE for license details. + +#ifndef _RISCV_TRACER_H +#define _RISCV_TRACER_H + +#include "processor.h" + +static inline void trace_opcode(processor_t* p, insn_bits_t opc, insn_t insn) { +} + +#endif -- 2.30.2