From 26e21abbf16325a8b82272d3687efe7e30b5c10a Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Tue, 12 May 2020 12:14:24 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 304] Define minimum viable interface
 set for 180nm ASIC

---
 0a/81f8ee6e85ce9b9f5af22015c8f5f29a5dbd67 | 65 +++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 0a/81f8ee6e85ce9b9f5af22015c8f5f29a5dbd67

diff --git a/0a/81f8ee6e85ce9b9f5af22015c8f5f29a5dbd67 b/0a/81f8ee6e85ce9b9f5af22015c8f5f29a5dbd67
new file mode 100644
index 0000000..616eb52
--- /dev/null
+++ b/0a/81f8ee6e85ce9b9f5af22015c8f5f29a5dbd67
@@ -0,0 +1,65 @@
+Return-path: <libre-riscv-dev-bounces@lists.libre-riscv.org>
+Envelope-to: publicinbox@libre-riscv.org
+Delivery-date: Tue, 12 May 2020 13:14:27 +0100
+Received: from localhost ([::1] helo=libre-riscv.org)
+	by libre-soc.org with esmtp (Exim 4.89)
+	(envelope-from <libre-riscv-dev-bounces@lists.libre-riscv.org>)
+	id 1jYTnm-0002SK-Dk; Tue, 12 May 2020 13:14:26 +0100
+Received: from localhost ([127.0.0.1] helo=bugs.libre-soc.org)
+ by libre-soc.org with esmtp (Exim 4.89)
+ (envelope-from <bugzilla-daemon@libre-soc.org>) id 1jYTnk-0002SD-CI
+ for libre-riscv-dev@lists.libre-riscv.org; Tue, 12 May 2020 13:14:24 +0100
+From: bugzilla-daemon@libre-soc.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Tue, 12 May 2020 12:14:24 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: yimmanuel3@gatech.edu
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: lkcl@lkcl.net
+X-Bugzilla-Flags: 
+X-Bugzilla-Changed-Fields: 
+Message-ID: <bug-304-13-63eQlCAD9f@https.bugs.libre-soc.org/>
+In-Reply-To: <bug-304-13@https.bugs.libre-soc.org/>
+References: <bug-304-13@https.bugs.libre-soc.org/>
+X-Bugzilla-URL: https://bugs.libre-soc.org/
+Auto-Submitted: auto-generated
+MIME-Version: 1.0
+Subject: [libre-riscv-dev] [Bug 304] Define minimum viable interface set for
+ 180nm ASIC
+X-BeenThere: libre-riscv-dev@lists.libre-riscv.org
+X-Mailman-Version: 2.1.23
+Precedence: list
+List-Id: Libre-RISCV General Development
+ <libre-riscv-dev.lists.libre-riscv.org>
+List-Unsubscribe: <http://lists.libre-riscv.org/mailman/options/libre-riscv-dev>, 
+ <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=unsubscribe>
+List-Archive: <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
+List-Post: <mailto:libre-riscv-dev@lists.libre-riscv.org>
+List-Help: <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=help>
+List-Subscribe: <http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev>, 
+ <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=subscribe>
+Reply-To: Libre-RISCV General Development
+ <libre-riscv-dev@lists.libre-riscv.org>
+Content-Type: text/plain; charset="utf-8"
+Content-Transfer-Encoding: base64
+Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org
+Sender: "libre-riscv-dev" <libre-riscv-dev-bounces@lists.libre-riscv.org>
+
+aHR0cHM6Ly9idWdzLmxpYnJlLXNvYy5vcmcvc2hvd19idWcuY2dpP2lkPTMwNAoKLS0tIENvbW1l
+bnQgIzUgZnJvbSBZZWhvd3NodWEgPHlpbW1hbnVlbDNAZ2F0ZWNoLmVkdT4gLS0tCk9LLiBJJ2xs
+IHRyeSBhbmQgaGF2ZSBpdCBmaW5pc2hlZCBieSBUaHVyc2RheSBhZnRlcm5vb24uCgotLSAKWW91
+IGFyZSByZWNlaXZpbmcgdGhpcyBtYWlsIGJlY2F1c2U6CllvdSBhcmUgb24gdGhlIENDIGxpc3Qg
+Zm9yIHRoZSBidWcuCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
+X19fCmxpYnJlLXJpc2N2LWRldiBtYWlsaW5nIGxpc3QKbGlicmUtcmlzY3YtZGV2QGxpc3RzLmxp
+YnJlLXJpc2N2Lm9yZwpodHRwOi8vbGlzdHMubGlicmUtcmlzY3Yub3JnL21haWxtYW4vbGlzdGlu
+Zm8vbGlicmUtcmlzY3YtZGV2Cg==
+
-- 
2.30.2