From 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 Mar 2019 08:10:02 -0700 Subject: [PATCH] Add shregmap -init_msb_first and use in synth_xilinx --- passes/techmap/shregmap.cc | 16 ++++++++++++++-- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index f20863ba0..6cd9082dc 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -34,7 +34,7 @@ struct ShregmapOptions { int minlen, maxlen; int keep_before, keep_after; - bool zinit, init, params, ffe; + bool zinit, init, params, ffe, init_msb_first; dict> ffcells; ShregmapTech *tech; @@ -48,6 +48,7 @@ struct ShregmapOptions init = false; params = false; ffe = false; + init_msb_first = false; tech = nullptr; } }; @@ -307,6 +308,8 @@ struct ShregmapWorker initval.push_back(State::S0); remove_init.insert(bit); } + if (opts.init_msb_first) + std::reverse(initval.begin(), initval.end()); first_cell->setParam("\\INIT", initval); } @@ -442,9 +445,13 @@ struct ShregmapPass : public Pass { log("\n"); log(" -init\n"); log(" map initialized registers to the shift reg, add an INIT parameter to\n"); - log(" generated cells with the initialization value. (first bit to shift out\n"); + log(" generated cells with the initialization value. (First bit to shift out\n"); log(" in LSB position)\n"); log("\n"); + log(" -init_msb_first\n"); + log(" same as -init, but INIT parameter to have first bit to shift out\n"); + log(" in MSB position.\n"); + log("\n"); log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); log("\n"); @@ -515,6 +522,11 @@ struct ShregmapPass : public Pass { opts.init = true; continue; } + if (args[argidx] == "-init_msb_first") { + opts.init = true; + opts.init_msb_first = true; + continue; + } if (args[argidx] == "-params") { opts.params = true; continue; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ce597ea4a..71b468e38 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -105,7 +105,7 @@ struct SynthXilinxPass : public Pass log(" dff2dffe\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); - log(" shregmap -init -params -enpol any_or_none\n"); + log(" shregmap -init_msb_first -params -enpol any_or_none\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -225,7 +225,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); - Pass::call(design, "shregmap -init -params -enpol any_or_none"); + Pass::call(design, "shregmap -init_msb_first -params -enpol any_or_none"); Pass::call(design, "opt -fast"); } -- 2.30.2