From 26ff0254b0a6168028285d03c03b9a75a721b28d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Jun 2019 15:56:05 +0100 Subject: [PATCH] compress table --- .../sv_prefix_proposal/discussion.rst | 38 +++++++++---------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/simple_v_extension/sv_prefix_proposal/discussion.rst b/simple_v_extension/sv_prefix_proposal/discussion.rst index 299832af8..9731c6ec8 100644 --- a/simple_v_extension/sv_prefix_proposal/discussion.rst +++ b/simple_v_extension/sv_prefix_proposal/discussion.rst @@ -264,24 +264,24 @@ experiment 1: experiment 2: -+-----------+-------------+------------+--------------+------------+-----------------------------------------------+ -| VLtyp[11] | VLtyp[10:6] | VLtyp[5] | VLtyp[4:3] | VLtyp[2:0] | comment | -+-----------+-------------+------------+--------------+------------+-----------------------------------------------+ -| 0 | 00000 | 0 00 | 000 | no change to VL/MVL | -+-----------+-------------+---------------------------+------------+-----------------------------------------------+ -| 0 | imm | 000 | rs'!=0 | MVL = imm; vl = min(r[rs'], MVL) | -+-----------+-------------+---------------------------+------------+-----------------------------------------------+ -| 0 | imm | rd'!=0 | 000 | MVL = imm; vl = MVL; r[rd'] = vl | -+-----------+-------------+---------------------------+------------+-----------------------------------------------+ -| 0 | imm | rd'!=0 | rs'!=0 | MVL = imm; vl = min(r[rs'], MVL); r[rd'] = vl | -+-----------+-------------+------------+--------------+------------+-----------------------------------------------+ -| 1 | imm | 0 | 00 000 | MVL = imm; vl = MVL; | -+-----------+-------------+------------+---------------------------+-----------------------------------------------+ -| 1 | imm | 0 | rd[4:0] | MVL = imm; vl = MVL; r[rd] = vl | -+-----------+-------------+------------+---------------------------+-----------------------------------------------+ -| 1 | imm | 1 | 00 000 | reserved | -+-----------+-------------+------------+---------------------------+-----------------------------------------------+ -| 1 | imm | 1 | rs1[4:0] | MVL = imm; vl = min(r[rs], MVL) | -+-----------+-------------+------------+---------------------------+-----------------------------------------------+ ++----+------+-----+-------+----------+-----------------------------------------------+ +| 11 | 10:6 | 5 | 4:3 | 2:0 | comment | ++----+------+-----+-------+----------+-----------------------------------------------+ +| 0 | 000 | 000 | 000 | no change to VL/MVL | ++----+------+-------------+----------+-----------------------------------------------+ +| 0 | imm | 000 | rs'!=0 | MVL = imm; vl = min(r[rs'], MVL) | ++----+------+-------------+----------+-----------------------------------------------+ +| 0 | imm | rd'!=0 | 000 | MVL = imm; vl = MVL; r[rd'] = vl | ++----+------+-------------+----------+-----------------------------------------------+ +| 0 | imm | rd'!=0 | rs'!=0 | MVL = imm; vl = min(r[rs'], MVL); r[rd'] = vl | ++----+------+-----+-------+----------+-----------------------------------------------+ +| 1 | imm | 0 | 00 000 | MVL = imm; vl = MVL; | ++----+------+-----+------------------+-----------------------------------------------+ +| 1 | imm | 0 | rd[4:0] | MVL = imm; vl = MVL; r[rd] = vl | ++----+------+-----+------------------+-----------------------------------------------+ +| 1 | imm | 1 | 00 000 | reserved | ++----+------+-----+------------------+-----------------------------------------------+ +| 1 | imm | 1 | rs1[4:0] | MVL = imm; vl = min(r[rs], MVL) | ++----+------+-----+------------------+-----------------------------------------------+ interestingly, "VLtyp[11] = 0" fits the sv.setvl pseudcode really well. -- 2.30.2