From 2701f887fc376202577ad942c20a7284b12823f3 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Mon, 27 Jul 2020 18:00:41 +0300 Subject: [PATCH] anv/nir: Unify inputs_read/outputs_written between geometry stages MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit inputs_read/outputs_written are used for a shader stage to determine the layout of input and output storage. Adjacent stages must agree on the layout, so adjacent input/output bitfields must match. Most of the time, cross-stage optimizations make that happen anyway, but there are some cases (with special values like clip distances and point size) where this doesn't happen. Fixes crashes in dEQP-VK.subgroups.*.framebuffer.*_tess_eval Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3210 Cc: Signed-off-by: Danylo Piliaiev Reviewed-by: Tapani Pälli Part-of: --- src/intel/vulkan/anv_pipeline.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 1b7c09f35a5..845451f7fc2 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1505,14 +1505,39 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline, void *stage_ctx = ralloc_context(NULL); + anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout); + + if (prev_stage && compiler->glsl_compiler_options[s].NirOptions->unify_interfaces) { + prev_stage->nir->info.outputs_written |= stages[s].nir->info.inputs_read & + ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER); + stages[s].nir->info.inputs_read |= prev_stage->nir->info.outputs_written & + ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER); + prev_stage->nir->info.patch_outputs_written |= stages[s].nir->info.patch_inputs_read; + stages[s].nir->info.patch_inputs_read |= prev_stage->nir->info.patch_outputs_written; + } + + ralloc_free(stage_ctx); + + stages[s].feedback.duration += os_time_get_nano() - stage_start; + + prev_stage = &stages[s]; + } + + prev_stage = NULL; + for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) { + if (!stages[s].entrypoint) + continue; + + int64_t stage_start = os_time_get_nano(); + + void *stage_ctx = ralloc_context(NULL); + nir_xfb_info *xfb_info = NULL; if (s == MESA_SHADER_VERTEX || s == MESA_SHADER_TESS_EVAL || s == MESA_SHADER_GEOMETRY) xfb_info = nir_gather_xfb_info(stages[s].nir, stage_ctx); - anv_pipeline_lower_nir(&pipeline->base, stage_ctx, &stages[s], layout); - switch (s) { case MESA_SHADER_VERTEX: anv_pipeline_compile_vs(compiler, stage_ctx, pipeline, -- 2.30.2