From 2714c0daad1d2618973c2f59f89a54da0056ed9b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 14:12:14 +0100 Subject: [PATCH] split out get_pred_value --- simple_v_extension/abridged_spec.mdwn | 33 ++------------------------ simple_v_extension/get_pred_value.mdwn | 13 ++++++++++ simple_v_extension/specification.mdwn | 13 +--------- 3 files changed, 16 insertions(+), 43 deletions(-) create mode 100644 simple_v_extension/get_pred_value.mdwn diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index 9400f9c1c..b9707d335 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -275,38 +275,9 @@ Mapping from 8 to 16 bit format, the table becomes: Pseudocode for predication: - struct pred { - bool zero; // zeroing - bool inv; // register at predidx is inverted - bool ffirst; // fail-on-first - bool enabled; // use this to tell if the table-entry is active - int predidx; // redirection: actual int register to use - } - struct pred fp_pred_reg[32]; - struct pred int_pred_reg[32]; - - for (i = 0; i < len; i++) // number of Predication entries in VBLOCK - tb = int_pred_reg if PredicateTable[i].type == 0 else fp_pred_reg; - idx = VBLOCKPredicateTable[i].regidx - tb[idx].zero = CSRpred[i].zero - tb[idx].inv = CSRpred[i].inv - tb[idx].ffirst = CSRpred[i].ffirst - tb[idx].predidx = CSRpred[i].predidx - tb[idx].enabled = true - - def get_pred_val(bool is_fp_op, int reg): - tb = int_reg if is_fp_op else fp_reg - if (!tb[reg].enabled): - return ~0x0, False // all enabled; no zeroing - tb = int_pred if is_fp_op else fp_pred - if (!tb[reg].enabled): - return ~0x0, False // all enabled; no zeroing - predidx = tb[reg].predidx // redirection occurs HERE - predicate = intreg[predidx] // actual predicate HERE - if (tb[reg].inv): - predicate = ~predicate // invert ALL bits - return predicate, tb[reg].zero +[[!inline raw="yes" pages="simple_v_extension/pred_table" ]] +[[!inline raw="yes" pages="simple_v_extension/get_pred_value" ]] ## Fail-on-First Mode diff --git a/simple_v_extension/get_pred_value.mdwn b/simple_v_extension/get_pred_value.mdwn new file mode 100644 index 000000000..65b9315ce --- /dev/null +++ b/simple_v_extension/get_pred_value.mdwn @@ -0,0 +1,13 @@ + def get_pred_val(bool is_fp_op, int reg): + tb = int_reg if is_fp_op else fp_reg + if (!tb[reg].enabled): + return ~0x0, False // all enabled; no zeroing + tb = int_pred if is_fp_op else fp_pred + if (!tb[reg].enabled): + return ~0x0, False // all enabled; no zeroing + predidx = tb[reg].predidx // redirection occurs HERE + predicate = intreg[predidx] // actual predicate HERE + if (tb[reg].inv): + predicate = ~predicate // invert ALL bits + return predicate, tb[reg].zero + diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 377296ca4..d59af335b 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -690,18 +690,7 @@ Note: If written as a function, obtaining the predication mask (and whether zeroing takes place) may be done as follows: - def get_pred_val(bool is_fp_op, int reg): - tb = int_reg if is_fp_op else fp_reg - if (!tb[reg].enabled): - return ~0x0, False // all enabled; no zeroing - tb = int_pred if is_fp_op else fp_pred - if (!tb[reg].enabled): - return ~0x0, False // all enabled; no zeroing - predidx = tb[reg].predidx // redirection occurs HERE - predicate = intreg[predidx] // actual predicate HERE - if (tb[reg].inv): - predicate = ~predicate // invert ALL bits - return predicate, tb[reg].zero +[[!inline raw="yes" pages="simple_v_extension/get_pred_value" ]] Note here, critically, that **only** if the register is marked in its **register** table entry as being "active" does the testing -- 2.30.2