From 2720cc47173b23e02cb9e08975919e40e75f6109 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Wed, 6 Oct 2010 08:16:18 +0000 Subject: [PATCH] mn10300.h (FIRST_PSEUDO_REGISTER): Increment by one. * config/mn10300/mn10300.h (FIRST_PSEUDO_REGISTER): Increment by one. (MDR_REGNUM): Define. (FIXED_REGISTERS, CALL_USED_REGISTERS): Add MDR as a fixed register. (REG_CLASS_CONTENTS): Add MDR to ALL_REGS. (INCOMING_RETURN_ADDR_RTX): Define in terms of MDR. (REGISTER_NAMES): Add MDR. (DWARF2_DEBUGGING_INFO): Define to 1. * config/mn10300/mn10300.c (TARGET_EXCEPT_UNWIND_INFO): Define. (F): New function. Sets RTX_FRAME_RELATED_P. (mn10300_gen_multiple_store): Use F. (expand_prologue): Use F. Use gen_movsf() to push floating point registers. (expand_epilogue): Use gen_movsf() to pop floating point registers. (mn10300_option_override): Disable combine stack adjust pass. From-SVN: r165015 --- gcc/ChangeLog | 20 +++++++++ gcc/config/mn10300/mn10300.c | 83 +++++++++++++++++++++--------------- gcc/config/mn10300/mn10300.h | 16 ++++--- 3 files changed, 78 insertions(+), 41 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 98b79df54e3..64c670af019 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2010-10-06 Nick Clifton + + * config/mn10300/mn10300.h (FIRST_PSEUDO_REGISTER): Increment by + one. + (MDR_REGNUM): Define. + (FIXED_REGISTERS, CALL_USED_REGISTERS): Add MDR as a fixed + register. + (REG_CLASS_CONTENTS): Add MDR to ALL_REGS. + (INCOMING_RETURN_ADDR_RTX): Define in terms of MDR. + (REGISTER_NAMES): Add MDR. + (DWARF2_DEBUGGING_INFO): Define to 1. + * config/mn10300/mn10300.c (TARGET_EXCEPT_UNWIND_INFO): Define. + (F): New function. Sets RTX_FRAME_RELATED_P. + (mn10300_gen_multiple_store): Use F. + (expand_prologue): Use F. Use gen_movsf() to push floating + point registers. + (expand_epilogue): Use gen_movsf() to pop floating point + registers. + (mn10300_option_override): Disable combine stack adjust pass. + 2010-10-06 Thomas Schwinge PR target/45901 diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index fe03742e7e4..47e5293b890 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -93,6 +93,9 @@ static void mn10300_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_ static bool mn10300_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); /* Initialize the GCC target structure. */ +#undef TARGET_EXCEPT_UNWIND_INFO +#define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info + #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" @@ -187,6 +190,12 @@ mn10300_option_override (void) { if (TARGET_AM33) target_flags &= ~MASK_MULT_BUG; + + /* FIXME: The combine stack adjustments pass is breaking + cc0-setter/cc0-user relationship by inserting a jump + instruction. This should be investigated, but for now + just disable the pass. */ + flag_combine_stack_adjustments = 0; } static void @@ -661,6 +670,13 @@ mn10300_get_live_callee_saved_regs (void) return mask; } +static rtx +F (rtx r) +{ + RTX_FRAME_RELATED_P (r) = 1; + return r; +} + /* Generate an instruction that pushes several registers onto the stack. Register K will be saved if bit K in MASK is set. The function does nothing if MASK is zero. @@ -702,11 +718,11 @@ mn10300_gen_multiple_store (int mask) /* Create the instruction that updates the stack pointer. */ XVECEXP (par, 0, 0) - = gen_rtx_SET (SImode, - stack_pointer_rtx, - gen_rtx_PLUS (SImode, - stack_pointer_rtx, - GEN_INT (-count * 4))); + = F (gen_rtx_SET (SImode, + stack_pointer_rtx, + gen_rtx_PLUS (SImode, + stack_pointer_rtx, + GEN_INT (-count * 4)))); /* Create each store. */ pari = 1; @@ -717,14 +733,13 @@ mn10300_gen_multiple_store (int mask) stack_pointer_rtx, GEN_INT (-pari * 4)); XVECEXP(par, 0, pari) - = gen_rtx_SET (VOIDmode, - gen_rtx_MEM (SImode, address), - gen_rtx_REG (SImode, i)); + = F (gen_rtx_SET (VOIDmode, + gen_rtx_MEM (SImode, address), + gen_rtx_REG (SImode, i))); pari += 1; } - par = emit_insn (par); - RTX_FRAME_RELATED_P (par) = 1; + F (emit_insn (par)); } } @@ -751,7 +766,6 @@ expand_prologue (void) save_a0_no_merge } strategy; unsigned int strategy_size = (unsigned)-1, this_strategy_size; rtx reg; - rtx insn; /* We have several different strategies to save FP registers. We can store them using SP offsets, which is beneficial if @@ -891,25 +905,25 @@ expand_prologue (void) { case save_sp_no_merge: case save_a0_no_merge: - emit_insn (gen_addsi3 (stack_pointer_rtx, - stack_pointer_rtx, - GEN_INT (-4 * num_regs_to_save))); + F (emit_insn (gen_addsi3 (stack_pointer_rtx, + stack_pointer_rtx, + GEN_INT (-4 * num_regs_to_save)))); xsize = 0; break; case save_sp_partial_merge: - emit_insn (gen_addsi3 (stack_pointer_rtx, - stack_pointer_rtx, - GEN_INT (-128))); + F (emit_insn (gen_addsi3 (stack_pointer_rtx, + stack_pointer_rtx, + GEN_INT (-128)))); xsize = 128 - 4 * num_regs_to_save; size -= xsize; break; case save_sp_merge: case save_a0_merge: - emit_insn (gen_addsi3 (stack_pointer_rtx, - stack_pointer_rtx, - GEN_INT (-(size + 4 * num_regs_to_save)))); + F (emit_insn (gen_addsi3 (stack_pointer_rtx, + stack_pointer_rtx, + GEN_INT (-(size + 4 * num_regs_to_save))))); /* We'll have to adjust FP register saves according to the frame size. */ xsize = size; @@ -934,9 +948,9 @@ expand_prologue (void) case save_a0_merge: case save_a0_no_merge: reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); - emit_insn (gen_movsi (reg, stack_pointer_rtx)); + F (emit_insn (gen_movsi (reg, stack_pointer_rtx))); if (xsize) - emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))); + F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)))); reg = gen_rtx_POST_INC (SImode, reg); break; @@ -967,22 +981,21 @@ expand_prologue (void) xsize += 4; } - insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr), - gen_rtx_REG (SImode, i))); - - RTX_FRAME_RELATED_P (insn) = 1; + F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr), + gen_rtx_REG (SFmode, i)))); } } /* Now put the frame pointer into the frame pointer register. */ if (frame_pointer_needed) - emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); + F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx)); /* Allocate stack for this frame. */ if (size) - emit_insn (gen_addsi3 (stack_pointer_rtx, - stack_pointer_rtx, - GEN_INT (-size))); + F (emit_insn (gen_addsi3 (stack_pointer_rtx, + stack_pointer_rtx, + GEN_INT (-size)))); + if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) emit_insn (gen_GOTaddr2picreg ()); } @@ -1169,8 +1182,8 @@ expand_epilogue (void) size += 4; - emit_insn (gen_movsi (gen_rtx_REG (SImode, i), - gen_rtx_MEM (SImode, addr))); + emit_insn (gen_movsf (gen_rtx_REG (SFmode, i), + gen_rtx_MEM (SFmode, addr))); } /* If we were using the restore_a1 strategy and the number of @@ -1261,8 +1274,8 @@ notice_update_cc (rtx body, rtx insn) /* The insn is a compare instruction. */ CC_STATUS_INIT; cc_status.value1 = SET_SRC (body); - if (GET_CODE (cc_status.value1) == COMPARE - && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode) + if (GET_CODE (SET_SRC (body)) == COMPARE + && GET_MODE (XEXP (SET_SRC (body), 0)) == SFmode) cc_status.mdep.fpCC = 1; break; @@ -2138,7 +2151,7 @@ mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRI bool mn10300_wide_const_load_uses_clr (rtx operands[2]) { - long val[2]; + long val[2] = {0, 0}; if (GET_CODE (operands[0]) != REG || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h index 56e2bc80792..26990adf50e 100644 --- a/gcc/config/mn10300/mn10300.h +++ b/gcc/config/mn10300/mn10300.h @@ -117,7 +117,7 @@ extern enum processor_type mn10300_processor; All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. */ -#define FIRST_PSEUDO_REGISTER 50 +#define FIRST_PSEUDO_REGISTER 51 /* Specify machine-specific register numbers. */ #define FIRST_DATA_REGNUM 0 @@ -128,6 +128,7 @@ extern enum processor_type mn10300_processor; #define LAST_EXTENDED_REGNUM 17 #define FIRST_FP_REGNUM 18 #define LAST_FP_REGNUM 49 +#define MDR_REGNUM 50 #define FIRST_ARGUMENT_REGNUM 0 /* Specify the registers used for certain standard purposes. @@ -153,7 +154,7 @@ extern enum processor_type mn10300_processor; #define FIXED_REGISTERS \ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 \ , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ - , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ + , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \ } /* 1 for registers not available across function calls. @@ -167,7 +168,7 @@ extern enum processor_type mn10300_processor; #define CALL_USED_REGISTERS \ { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 \ , 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ - , 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ + , 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* Note: The definition of CALL_REALLY_USED_REGISTERS is not @@ -298,7 +299,7 @@ enum reg_class { { 0xfffc0000, 0x3ffff }, /* FP_REGS */ \ { 0x03fc0000, 0 }, /* FP_ACC_REGS */ \ { 0x3fdff, 0 }, /* GENERAL_REGS */ \ - { 0xffffffff, 0x3ffff } /* ALL_REGS */ \ + { 0xffffffff, 0x7ffff } /* ALL_REGS */ \ } /* The following macro defines cover classes for Integrated Register @@ -587,6 +588,8 @@ struct cum_arg {int nbytes; }; ((COUNT == 0) \ ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ : (rtx) 0) + +#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, MDR_REGNUM) /* Maximum number of registers that can appear in a valid memory address. */ @@ -765,7 +768,7 @@ struct cum_arg {int nbytes; }; , "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \ , "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \ , "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \ -, "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \ + , "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31", "mdr" \ } #define ADDITIONAL_REGISTER_NAMES \ @@ -810,8 +813,9 @@ struct cum_arg {int nbytes; }; #define DEFAULT_GDB_EXTENSIONS 1 /* Use dwarf2 debugging info by default. */ -#undef PREFERRED_DEBUGGING_TYPE +#undef PREFERRED_DEBUGGING_TYPE #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +#define DWARF2_DEBUGGING_INFO 1 #define DWARF2_ASM_LINE_DEBUG_INFO 1 -- 2.30.2