From 272e12eb177c662826f901d536f685a4abf62123 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 26 Jun 2017 10:00:34 -0700 Subject: [PATCH] Move target definition into individual files. Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa. --- debug/Makefile | 2 +- debug/README.md | 48 +++-- debug/gdbserver.py | 2 +- debug/targets.py | 185 +++++++----------- .../openocd.cfg => RISC-V/spike32.cfg} | 0 .../{spike32/link.lds => RISC-V/spike32.lds} | 0 debug/targets/RISC-V/spike32.py | 12 ++ .../openocd.cfg => RISC-V/spike64.cfg} | 0 .../{spike64/link.lds => RISC-V/spike64.lds} | 0 debug/targets/RISC-V/spike64.py | 12 ++ debug/targets/SiFive/Freedom/E300.py | 9 + debug/targets/SiFive/Freedom/E300Sim.py | 13 ++ .../Freedom/Freedom.cfg} | 0 .../link.lds => SiFive/Freedom/Freedom.lds} | 0 debug/targets/SiFive/Freedom/U500.py | 9 + debug/targets/SiFive/Freedom/U500Sim.py | 11 ++ .../openocd.cfg => SiFive/HiFive1.cfg} | 0 .../link.lds => SiFive/HiFive1.lds} | 0 debug/targets/SiFive/HiFive1.py | 8 + debug/targets/freedom-e300-sim/openocd.cfg | 15 -- debug/targets/freedom-e300/link.lds | 34 ---- debug/targets/freedom-e300/openocd.cfg | 16 -- debug/targets/freedom-u500-sim/link.lds | 34 ---- debug/targets/freedom-u500-sim/openocd.cfg | 15 -- debug/targets/freedom-u500/link.lds | 34 ---- debug/testlib.py | 9 +- 26 files changed, 184 insertions(+), 284 deletions(-) rename debug/targets/{spike32/openocd.cfg => RISC-V/spike32.cfg} (100%) rename debug/targets/{spike32/link.lds => RISC-V/spike32.lds} (100%) create mode 100644 debug/targets/RISC-V/spike32.py rename debug/targets/{spike64/openocd.cfg => RISC-V/spike64.cfg} (100%) rename debug/targets/{spike64/link.lds => RISC-V/spike64.lds} (100%) create mode 100644 debug/targets/RISC-V/spike64.py create mode 100644 debug/targets/SiFive/Freedom/E300.py create mode 100644 debug/targets/SiFive/Freedom/E300Sim.py rename debug/targets/{freedom-u500/openocd.cfg => SiFive/Freedom/Freedom.cfg} (100%) rename debug/targets/{HiFive1/link.lds => SiFive/Freedom/Freedom.lds} (100%) mode change 100755 => 100644 create mode 100644 debug/targets/SiFive/Freedom/U500.py create mode 100644 debug/targets/SiFive/Freedom/U500Sim.py rename debug/targets/{HiFive1/openocd.cfg => SiFive/HiFive1.cfg} (100%) rename debug/targets/{freedom-e300-sim/link.lds => SiFive/HiFive1.lds} (100%) create mode 100644 debug/targets/SiFive/HiFive1.py delete mode 100644 debug/targets/freedom-e300-sim/openocd.cfg delete mode 100755 debug/targets/freedom-e300/link.lds delete mode 100644 debug/targets/freedom-e300/openocd.cfg delete mode 100755 debug/targets/freedom-u500-sim/link.lds delete mode 100644 debug/targets/freedom-u500-sim/openocd.cfg delete mode 100755 debug/targets/freedom-u500/link.lds diff --git a/debug/Makefile b/debug/Makefile index f835507..c5ea991 100644 --- a/debug/Makefile +++ b/debug/Makefile @@ -14,7 +14,7 @@ pylint: %.log: $(GDBSERVER_PY) \ --isolate \ - --$(subst .log,,$@) \ + targets/RISC-V/$(subst .log,.py,$@) \ --sim_cmd $(RISCV)/bin/$(RISCV_SIM) \ --server_cmd $(RISCV)/bin/openocd \ | tee $@ 2>&1 || (sed s/^/$@:\ / $@ && false) diff --git a/debug/README.md b/debug/README.md index 04aa13a..1a802cf 100644 --- a/debug/README.md +++ b/debug/README.md @@ -12,37 +12,47 @@ Targets 64-bit Spike ------------ -`./gdbserver.py --spike64 --cmd $RISCV/bin/spike` +`./gdbserver.py targets/RISC-V/spike64.py` 32-bit Spike ------------ -`./gdbserver.py --spike32 --cmd $RISCV/bin/spike` +`./gdbserver.py targets/RISC-V/spike32.py` -32-bit SiFive Core on Supported FPGA Boards & Hardware -------------------------------------- +32-bit SiFive Core on Supported FPGA Boards & Hardware +------------------------------------------------------ -`./gdbserver.py --freedom-e300` -`./gdbserver.py --hifive1` +`./gdbserver.py targets/SiFive/E300.py` +`./gdbserver.py targets/SiFive/HiFive1.py` +Custom Target +------------- -32-bit rocket-chip core in Simulation -------------------------------------- +For custom targets, you can create a .py file anywhere and pass its path on the +command line. The Targets class in `targets.py` contains documentation on what +every variable means. -`./gdbserver.py --freedom-e300-sim` + +Log Files +========= + +All output from tests ends up in the `logs/` subdirectory, with one log file +per test. If a test fails, this is where to look. Debug Tips ========== -You can run just a single test by specifying . on the command -line, eg: `./gdbserver.py --spike64 --cmd $RISCV/bin/spike -SimpleRegisterTest.test_s0`. -Once that test has failed, you can look at gdb.log and (in this case) spike.log -to get an idea of what might have gone wrong. +You can run just a single test by specifying any part of its name on the +command line, eg: `./gdbserver.py targets/RISC-V/spike64.py S0` runs +SimpleS0Test. Once that test has failed, you can look at the log file to get +an idea of what might have gone wrong. + +You can see what spike is doing by adding `-l` to the spike command, eg.: +`./gdbserver.py --sim_cmd "$RISCV/bin/spike -l" targets/RISC-V/spike32.py Breakpoint` -You can see what spike is doing by add `-l` to the spike command, eg.: -`./gdbserver.py --spike32 --cmd "$RISCV/bin/spike -l" -DebugTest.test_breakpoint`. (Then look at spike.log.) +You can see what OpenOCD is doing by adding `-d` to the OpenOCD command, eg.: +`./gdbserver.py --server_cmd "openocd -d" targets/RISC-V/spike32.py Breakpoint` -You can run gdb under valgrind by passing --gdb, eg.: `./gdbserver.py --spike64 ---gdb "valgrind riscv64-unknown-elf-gdb" -- -v DownloadTest`. +You can run gdb under valgrind by passing --gdb, eg.: `./gdbserver.py +--gdb "valgrind riscv64-unknown-elf-gdb" targets/RISC-V/spike64.py +DownloadTest` diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 2dcd404..37fd698 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -757,8 +757,8 @@ def main(): # TODO: remove global global parsed # pylint: disable=global-statement parsed = parser.parse_args() + target = targets.target(parsed) - target = parsed.target(parsed.server_cmd, parsed.sim_cmd, parsed.isolate) if parsed.xlen: target.xlen = parsed.xlen diff --git a/debug/targets.py b/debug/targets.py index 525561e..1f4b176 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -1,35 +1,68 @@ +import importlib import os.path +import sys import tempfile import testlib class Target(object): - name = "name" + # pylint: disable=too-many-instance-attributes + + # Name of the target. Defaults to the name of the class. + name = None + + # XLEN of the target. May be overridden with --32 or --64 command line + # options. xlen = 0 - directory = None + + # GDB remotetimeout setting. timeout_sec = 2 - temporary_files = [] - temporary_binary = None - openocd_config = [] - use_fpu = False + + # Path to OpenOCD configuration file relative to the .py file where the + # target is defined. Defaults to .cfg. + openocd_config_path = None + + # Path to linker script relative to the .py file where the target is + # defined. Defaults to .lds. + link_script_path = None + + # Will be autodetected (by running ExamineTarget) if left unset. Set to + # save a little time. misa = None - def __init__(self, server_cmd, sim_cmd, isolate): - self.server_cmd = server_cmd - self.sim_cmd = sim_cmd - self.isolate = isolate + # Internal variables: + directory = None + temporary_files = [] + temporary_binary = None - def target(self): - """Start the target, eg. a simulator.""" + def __init__(self, path, parsed): + # Path to module. + self.path = path + self.directory = os.path.dirname(path) + self.server_cmd = parsed.server_cmd + self.sim_cmd = parsed.sim_cmd + self.isolate = parsed.isolate + if not self.name: + self.name = type(self).__name__ + # Default OpenOCD config file to .cfg + if not self.openocd_config_path: + self.openocd_config_path = "%s.cfg" % self.name + self.openocd_config_path = os.path.join(self.directory, + self.openocd_config_path) + # Default link script to .lds + if not self.link_script_path: + self.link_script_path = "%s.lds" % self.name + self.link_script_path = os.path.join(self.directory, + self.link_script_path) + + def create(self): + """Create the target out of thin air, eg. start a simulator.""" pass def server(self): """Start the debug server that gdb connects to, eg. OpenOCD.""" - if self.openocd_config: - return testlib.Openocd(server_cmd=self.server_cmd, - config=self.openocd_config) - else: - raise NotImplementedError + return testlib.Openocd(server_cmd=self.server_cmd, + config=self.openocd_config_path) def compile(self, *sources): binary_name = "%s_%s-%d" % ( @@ -42,15 +75,14 @@ class Target(object): binary_name = self.temporary_binary.name Target.temporary_files.append(self.temporary_binary) march = "rv%dima" % self.xlen - if self.use_fpu: - march += "fd" - if self.extensionSupported("c"): - march += "c" + for letter in "fdc": + if self.extensionSupported(letter): + march += letter testlib.compile(sources + ("programs/entry.S", "programs/init.c", "-I", "../env", "-march=%s" % march, - "-T", "targets/%s/link.lds" % (self.directory or self.name), + "-T", self.link_script_path, "-nostartfiles", "-mcmodel=medany", "-DXLEN=%d" % self.xlen, @@ -65,98 +97,12 @@ class Target(object): else: return False -class SpikeTarget(Target): - # pylint: disable=abstract-method - instruction_hardware_breakpoint_count = 4 - reset_vector = 0x1000 - -class Spike64Target(SpikeTarget): - name = "spike64" - directory = name - xlen = 64 - use_fpu = True - # Would like to use 0x7fffffffffff0000 because it crosses the 0x8000... - # boundary, but spike doesn't support that in the code where it generates - # the reset vector. - ram = 0x1212340000 - ram_size = 0x10000000 - openocd_config = "targets/%s/openocd.cfg" % directory - - def target(self): - return testlib.Spike(self) - -class Spike32Target(SpikeTarget): - name = "spike32" - directory = name - xlen = 32 - ram = 0x10000000 - ram_size = 0x10000000 - openocd_config = "targets/%s/openocd.cfg" % directory - - def target(self): - return testlib.Spike(self) - -class FreedomE300Target(Target): - name = "freedom-e300" - xlen = 32 - ram = 0x80000000 - ram_size = 16 * 1024 - instruction_hardware_breakpoint_count = 2 - openocd_config = "targets/%s/openocd.cfg" % name - -class HiFive1Target(FreedomE300Target): - name = "HiFive1" - openocd_config = "targets/%s/openocd.cfg" % name - -class FreedomE300SimTarget(Target): - name = "freedom-e300-sim" - xlen = 32 - timeout_sec = 6000 - ram = 0x80000000 - ram_size = 256 * 1024 * 1024 - instruction_hardware_breakpoint_count = 2 - openocd_config = "targets/%s/openocd.cfg" % name - - def target(self): - return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) - -class FreedomU500Target(Target): - name = "freedom-u500" - xlen = 64 - ram = 0x80000000 - ram_size = 16 * 1024 - instruction_hardware_breakpoint_count = 2 - openocd_config = "targets/%s/openocd.cfg" % name - -class FreedomU500SimTarget(Target): - name = "freedom-u500-sim" - xlen = 64 - timeout_sec = 6000 - ram = 0x80000000 - ram_size = 256 * 1024 * 1024 - instruction_hardware_breakpoint_count = 2 - openocd_config = "targets/%s/openocd.cfg" % name - - def target(self): - return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) - -targets = [ - Spike32Target, - Spike64Target, - FreedomE300Target, - FreedomU500Target, - FreedomE300SimTarget, - FreedomU500SimTarget, - HiFive1Target] - def add_target_options(parser): - group = parser.add_mutually_exclusive_group(required=True) - for t in targets: - group.add_argument("--%s" % t.name, action="store_const", const=t, - dest="target") + parser.add_argument("target", help=".py file that contains definition for " + "the target to test with.") parser.add_argument("--sim_cmd", help="The command to use to start the actual target (e.g. " - "simulation)") + "simulation)", default="spike") parser.add_argument("--server_cmd", help="The command to use to start the debug server (e.g. OpenOCD)") @@ -170,3 +116,20 @@ def add_target_options(parser): help="Try to run in such a way that multiple instances can run at " "the same time. This may make it harder to debug a failure if it " "does occur.") + +def target(parsed): + directory = os.path.dirname(parsed.target) + filename = os.path.basename(parsed.target) + module_name = os.path.splitext(filename)[0] + + sys.path.append(directory) + module = importlib.import_module(module_name) + found = [] + for name in dir(module): + definition = getattr(module, name) + if type(definition) == type and issubclass(definition, Target): + found.append(definition) + assert len(found) == 1, "%s does not define exactly one subclass of " \ + "targets.Target" % parsed.target + + return found[0](parsed.target, parsed) diff --git a/debug/targets/spike32/openocd.cfg b/debug/targets/RISC-V/spike32.cfg similarity index 100% rename from debug/targets/spike32/openocd.cfg rename to debug/targets/RISC-V/spike32.cfg diff --git a/debug/targets/spike32/link.lds b/debug/targets/RISC-V/spike32.lds similarity index 100% rename from debug/targets/spike32/link.lds rename to debug/targets/RISC-V/spike32.lds diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py new file mode 100644 index 0000000..3bf8b47 --- /dev/null +++ b/debug/targets/RISC-V/spike32.py @@ -0,0 +1,12 @@ +import targets +import testlib + +class spike32(targets.Target): + xlen = 32 + ram = 0x10000000 + ram_size = 0x10000000 + instruction_hardware_breakpoint_count = 4 + reset_vector = 0x1000 + + def create(self): + return testlib.Spike(self) diff --git a/debug/targets/spike64/openocd.cfg b/debug/targets/RISC-V/spike64.cfg similarity index 100% rename from debug/targets/spike64/openocd.cfg rename to debug/targets/RISC-V/spike64.cfg diff --git a/debug/targets/spike64/link.lds b/debug/targets/RISC-V/spike64.lds similarity index 100% rename from debug/targets/spike64/link.lds rename to debug/targets/RISC-V/spike64.lds diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py new file mode 100644 index 0000000..c705857 --- /dev/null +++ b/debug/targets/RISC-V/spike64.py @@ -0,0 +1,12 @@ +import targets +import testlib + +class spike64(targets.Target): + xlen = 64 + ram = 0x1212340000 + ram_size = 0x10000000 + instruction_hardware_breakpoint_count = 4 + reset_vector = 0x1000 + + def create(self): + return testlib.Spike(self) diff --git a/debug/targets/SiFive/Freedom/E300.py b/debug/targets/SiFive/Freedom/E300.py new file mode 100644 index 0000000..95ddcfd --- /dev/null +++ b/debug/targets/SiFive/Freedom/E300.py @@ -0,0 +1,9 @@ +import targets + +class E300(targets.Target): + xlen = 32 + ram = 0x80000000 + ram_size = 16 * 1024 + instruction_hardware_breakpoint_count = 2 + openocd_config_path = "Freedom.cfg" + link_script_path = "Freedom.lds" diff --git a/debug/targets/SiFive/Freedom/E300Sim.py b/debug/targets/SiFive/Freedom/E300Sim.py new file mode 100644 index 0000000..e98c5b9 --- /dev/null +++ b/debug/targets/SiFive/Freedom/E300Sim.py @@ -0,0 +1,13 @@ +import targets + +class E300Sim(targets.Target): + xlen = 32 + timeout_sec = 6000 + ram = 0x80000000 + ram_size = 256 * 1024 * 1024 + instruction_hardware_breakpoint_count = 2 + openocd_config_path = "Freedom.cfg" + link_script_path = "Freedom.lds" + + def target(self): + return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) diff --git a/debug/targets/freedom-u500/openocd.cfg b/debug/targets/SiFive/Freedom/Freedom.cfg similarity index 100% rename from debug/targets/freedom-u500/openocd.cfg rename to debug/targets/SiFive/Freedom/Freedom.cfg diff --git a/debug/targets/HiFive1/link.lds b/debug/targets/SiFive/Freedom/Freedom.lds old mode 100755 new mode 100644 similarity index 100% rename from debug/targets/HiFive1/link.lds rename to debug/targets/SiFive/Freedom/Freedom.lds diff --git a/debug/targets/SiFive/Freedom/U500.py b/debug/targets/SiFive/Freedom/U500.py new file mode 100644 index 0000000..c22aa4c --- /dev/null +++ b/debug/targets/SiFive/Freedom/U500.py @@ -0,0 +1,9 @@ +import targets + +class U500(targets.Target): + xlen = 64 + ram = 0x80000000 + ram_size = 16 * 1024 + instruction_hardware_breakpoint_count = 2 + openocd_config_path = "Freedom.cfg" + link_script_path = "Freedom.lds" diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py new file mode 100644 index 0000000..7648960 --- /dev/null +++ b/debug/targets/SiFive/Freedom/U500Sim.py @@ -0,0 +1,11 @@ +class U500Sim(Target): + xlen = 64 + timeout_sec = 6000 + ram = 0x80000000 + ram_size = 256 * 1024 * 1024 + instruction_hardware_breakpoint_count = 2 + openocd_config_path = "Freedom.cfg" + link_script_path = "Freedom.lds" + + def target(self): + return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) diff --git a/debug/targets/HiFive1/openocd.cfg b/debug/targets/SiFive/HiFive1.cfg similarity index 100% rename from debug/targets/HiFive1/openocd.cfg rename to debug/targets/SiFive/HiFive1.cfg diff --git a/debug/targets/freedom-e300-sim/link.lds b/debug/targets/SiFive/HiFive1.lds similarity index 100% rename from debug/targets/freedom-e300-sim/link.lds rename to debug/targets/SiFive/HiFive1.lds diff --git a/debug/targets/SiFive/HiFive1.py b/debug/targets/SiFive/HiFive1.py new file mode 100644 index 0000000..813829e --- /dev/null +++ b/debug/targets/SiFive/HiFive1.py @@ -0,0 +1,8 @@ +import targets + +class HiFive1(targets.Target): + xlen = 32 + ram = 0x80000000 + ram_size = 16 * 1024 + instruction_hardware_breakpoint_count = 2 + misa = 0x40001105 diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg deleted file mode 100644 index 5733f27..0000000 --- a/debug/targets/freedom-e300-sim/openocd.cfg +++ /dev/null @@ -1,15 +0,0 @@ -adapter_khz 10000 - -source [find interface/jtag_vpi.cfg] -jtag_vpi_set_port $::env(JTAG_VPI_PORT) -#jtag_vpi_set_port 34448 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv - -init -halt -echo "Ready for Remote Connections" diff --git a/debug/targets/freedom-e300/link.lds b/debug/targets/freedom-e300/link.lds deleted file mode 100755 index 1e0645a..0000000 --- a/debug/targets/freedom-e300/link.lds +++ /dev/null @@ -1,34 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -SECTIONS -{ - . = 0x80000000; - .text : - { - *(.text.entry) - *(.text) - } - - /* data segment */ - .data : { *(.data) } - - .sdata : { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - } - - /* bss segment */ - .sbss : { - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } - .bss : { *(.bss) } - - __malloc_start = .; - . = . + 512; - - /* End of uninitalized data segement */ - _end = .; -} diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg deleted file mode 100644 index 87c977a..0000000 --- a/debug/targets/freedom-e300/openocd.cfg +++ /dev/null @@ -1,16 +0,0 @@ -adapter_khz 10000 - -source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv - -gdb_report_data_abort enable - -init - -halt -echo "Ready for Remote Connections" diff --git a/debug/targets/freedom-u500-sim/link.lds b/debug/targets/freedom-u500-sim/link.lds deleted file mode 100755 index 1e0645a..0000000 --- a/debug/targets/freedom-u500-sim/link.lds +++ /dev/null @@ -1,34 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -SECTIONS -{ - . = 0x80000000; - .text : - { - *(.text.entry) - *(.text) - } - - /* data segment */ - .data : { *(.data) } - - .sdata : { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - } - - /* bss segment */ - .sbss : { - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } - .bss : { *(.bss) } - - __malloc_start = .; - . = . + 512; - - /* End of uninitalized data segement */ - _end = .; -} diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg deleted file mode 100644 index 5fba211..0000000 --- a/debug/targets/freedom-u500-sim/openocd.cfg +++ /dev/null @@ -1,15 +0,0 @@ -adapter_khz 10000 - -source [find interface/jtag_vpi.cfg] -jtag_vpi_set_port $::env(JTAG_VPI_PORT) - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv - -init - -halt -echo "Ready for Remote Connections" diff --git a/debug/targets/freedom-u500/link.lds b/debug/targets/freedom-u500/link.lds deleted file mode 100755 index 1e0645a..0000000 --- a/debug/targets/freedom-u500/link.lds +++ /dev/null @@ -1,34 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -SECTIONS -{ - . = 0x80000000; - .text : - { - *(.text.entry) - *(.text) - } - - /* data segment */ - .data : { *(.data) } - - .sdata : { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) - *(.srodata*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - } - - /* bss segment */ - .sbss : { - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } - .bss : { *(.bss) } - - __malloc_start = .; - . = . + 512; - - /* End of uninitalized data segement */ - _end = .; -} diff --git a/debug/testlib.py b/debug/testlib.py index b59e6e8..f511088 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -261,7 +261,7 @@ class Openocd(object): try: self.process.kill() self.process.wait() - except OSError: + except (OSError, AttributeError): pass class OpenocdCli(object): @@ -416,8 +416,9 @@ def run_all_tests(module, target, parsed): todo = [] if parsed.misaval: target.misa = int(parsed.misaval, 16) - print "Assuming $MISA value of 0x%x. Skipping ExamineTarget." % \ - target.misa + print "Using $misa from command line: 0x%x" % target.misa + elif target.misa: + print "Using $misa from target definition: 0x%x" % target.misa else: todo.append(("ExamineTarget", ExamineTarget)) @@ -538,7 +539,7 @@ class BaseTest(object): def classSetup(self): self.compile() - self.target_process = self.target.target() + self.target_process = self.target.create() self.server = self.target.server() self.logs.append(self.server.logname) -- 2.30.2