From 273e99cddd8c5ca884c9f46e82d9ce36ff8e8924 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 13 Oct 2020 05:46:27 +0100
Subject: [PATCH]

---
 openpower/openpower/sv/predication.mdwn | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 openpower/openpower/sv/predication.mdwn

diff --git a/openpower/openpower/sv/predication.mdwn b/openpower/openpower/sv/predication.mdwn
new file mode 100644
index 000000000..5b026cf54
--- /dev/null
+++ b/openpower/openpower/sv/predication.mdwn
@@ -0,0 +1,7 @@
+# TODO
+
+* idea 1: modify cmp (and other CR generators?) with qualifiers that create single bit prefix vector into int reg
+* idea 2: override CR SO field in vector form to be predicate bit per element
+* idea 3: reading of predicates is from bits of int reg
+* idea 4: SO CR field no longer overflow, contains copy of int reg predicate element bit (passed through).  when OE set?
+
-- 
2.30.2