From 274cab2ecd1a0c0ba3620789cbab7ab30510bb7d Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 7 May 2022 12:42:18 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index e92228cb1..f64d893d2 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -400,7 +400,8 @@ ISA, the amount of data processing requested and controlled by each instruction is enormous, and leaves the Decode and Issue Engines idle, as well as the L1 I-Cache. With programs being smaller, chances are higher that they fit into -L1 Cache, or that the L1 Cache may be made smaller. +L1 Cache, or that the L1 Cache may be made smaller: either way +is a considerable O(N^2) power-saving. Even a Packed SIMD ISA could take limited advantage of a higher bang-per-buck for limited specific workloads, as long as the -- 2.30.2