From 274f8a0177da2a7db28f1f9681654173271a84f5 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 30 Dec 2020 16:22:35 +0000 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index b9ab8b408..a88a4705c 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -348,7 +348,7 @@ but select different *bits* of the same CRs # Extra Remapped Encoding -Shows all instruction-specific fields in the Remapped Encoding `RM[8:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. +Shows all instruction-specific fields in the Remapped Encoding `RM[8:18]` for all instruction variants. Note that due to the very tight space, the encoding mode is *not* included in the prefix itself. The mode is "applied", similar to OpenPOWER "Forms" (X-Form, D-Form) on a per-instruction basis, and, like "Forms" are given a designation (below) of the form `RM-nP-nSnD`. The full list of which instructions use which remaps is here [[opcode_regs_deduped]]. (*Machine-readable CSV files have been provided which will make the task of creating SV-aware ISA decoders easier*). There are two categories: Single and Twin Predication. Due to space considerations further subdivision of Single Predication -- 2.30.2