From 27547e8fad40836704f0902ce12b61170406be81 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 6 Oct 2022 12:57:57 +0100 Subject: [PATCH] add vli mode to ff=5 CR ops --- src/openpower/sv/trans/svp64.py | 11 ++++++++--- src/openpower/sv/trans/test_pysvp64dis.py | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 1665087d..45f212c2 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -1386,6 +1386,9 @@ class SVP64Asm: assert dst_zero == src_zero, "dz must equal sz in ffirst BO" mode |= (failfirst << SVP64MODE.BO_LSB) # set BO svp64_rm.crops.zz = dst_zero + if vli: + sv_mode |= 1 # set VLI in LSB of 2-bit mode + #svp64_rm.cr_op.vli = 1 ###################################### # "saturation" modes @@ -1422,17 +1425,19 @@ class SVP64Asm: if sea: mode |= (0b1 << SVP64MODE.SEA) + # this is a mess. really look forward to replacing it with Insn DB if not is_bc: svp64_rm.mode = mode # mode: bits 19-23 - if vli: + if vli and not is_cr: svp64_rm.normal.ffrc0.VLi = 1 # put in predicate masks into svp64_rm if ptype == '2P': svp64_rm.smask = smask # source pred: bits 16-18 - # put in elwidths unless bc - svp64_rm.ewsrc = srcwid # srcwid: bits 6-7 + # put in elwidths unless cr + if not is_cr: + svp64_rm.ewsrc = srcwid # srcwid: bits 6-7 svp64_rm.elwidth = destwid # destwid: bits 4-5 svp64_rm.mmode = mmode # mask mode: bit 0 diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 794f3ee0..e76819b4 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -308,6 +308,7 @@ class SVSTATETestCase(unittest.TestCase): expected = [ "sv.cmp *4,1,*0,1", "sv.cmp/ff=RC1 *4,1,*0,1", + "sv.cmp/ff=RC1/vli *4,1,*0,1", "sv.cmp/ff=~RC1 *4,1,*0,1", "sv.cmp/ff=RC1/m=r3/sz *4,1,*0,1", "sv.cmp/dz/ff=RC1/m=r3 *4,1,*0,1", -- 2.30.2