From 27674e3a207328cfab6d2496c157d9ccd09671d7 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 18 Sep 2022 14:25:40 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index f9008ab81..f737d800c 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -78,10 +78,10 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations: | 6 | 7 | 19-20 | 21 | 22 23 | description | | - | - |-------| --- |---------|----------------- | -|sz |SNZ| 0 RG | 0 | dz / | simple mode | -|sz |SNZ| 0 RG | 1 | 0 / | scalar reduce mode (mapreduce) | +| / |SNZ| 0 RG | 0 | dz sz | simple mode | +| / |SNZ| 0 RG | 1 | dz sz | scalar reduce mode (mapreduce) | |zz |SNZ| 1 VLI | inv | CR-bit | Ffirst 3-bit mode | -|sz |SNZ| 1 VLI | inv | dz / | Ffirst 5-bit mode | +| / |SNZ| 1 VLI | inv | dz sz | Ffirst 5-bit mode | Fields: -- 2.30.2