From 279ea105d8e91aa922ad946b66ee076e5e7e21c7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 2 May 2008 10:51:40 -0400 Subject: [PATCH] R5xx: various updates - fixup VAP_CNTL setup - remove extra instruction in r5xx passthrough shader - add notes about pipe config --- src/mesa/drivers/dri/r300/r300_reg.h | 9 ++- src/mesa/drivers/dri/r300/r300_state.c | 71 ++++++++++++--------- src/mesa/drivers/dri/radeon/radeon_screen.c | 9 ++- 3 files changed, 56 insertions(+), 33 deletions(-) diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h index 2822b1d4c3a..fee21dae674 100644 --- a/src/mesa/drivers/dri/r300/r300_reg.h +++ b/src/mesa/drivers/dri/r300/r300_reg.h @@ -70,6 +70,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Stolen from r200 code from Christoph Brill (It's a guess!) */ #define R300_VAP_CNTL 0x2080 +# define R300_PVS_NUM_SLOTS_SHIFT 0 +# define R300_PVS_NUM_CNTLRS_SHIFT 4 +# define R300_PVS_NUM_FPUS_SHIFT 8 +# define R300_VF_MAX_VTX_NUM_SHIFT 18 +# define R300_GL_CLIP_SPACE_DEF (0 << 22) +# define R300_DX_CLIP_SPACE_DEF (1 << 22) +# define R500_TCL_STATE_OPTIMIZATION (1 << 23) /* This register is written directly and also starts data section * in many 3d CP_PACKET3's @@ -375,7 +382,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_VAP_CLIP_CNTL 0x221C # define R300_221C_NORMAL 0x00000000 # define R300_221C_CLEAR 0x0001C000 -#define R300_VAP_UCP_ENABLE_0 (1 << 0) +# define R300_VAP_UCP_ENABLE_0 (1 << 0) /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first * plane is per-pixel and the second plane is per-vertex. diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 7419b15a55c..0740d7ea4a4 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1981,10 +1981,34 @@ static void r300ResetHwState(r300ContextPtr r300) r300AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef); r300Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled); - if (!has_tcl) - r300->hw.vap_cntl.cmd[1] = 0x0014045a; + /* setup the VAP */ + /* PVS_NUM_SLOTS, PVS_NUM_CNTLRS, VF_MAX_VTX_NUM need to be adjusted + * dynamically. PVS_NUM_FPUS is fixed based on asic + */ + if (has_tcl) { + r300->hw.vap_cntl.cmd[1] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | + (5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (12 << R300_VF_MAX_VTX_NUM_SHIFT)); + if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) + r300->hw.vap_cntl.cmd[1] |= R500_TCL_STATE_OPTIMIZATION; + } else + r300->hw.vap_cntl.cmd[1] = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | + (5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (5 << R300_VF_MAX_VTX_NUM_SHIFT)); + + if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) + r300->hw.vap_cntl.cmd[1] |= (2 << R300_PVS_NUM_FPUS_SHIFT); + else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) || + (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV560)) + r300->hw.vap_cntl.cmd[1] |= (5 << R300_PVS_NUM_FPUS_SHIFT); + else if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R420) + r300->hw.vap_cntl.cmd[1] |= (6 << R300_PVS_NUM_FPUS_SHIFT); + else if ((r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R520) || + (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_R580) || + (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV570)) + r300->hw.vap_cntl.cmd[1] |= (8 << R300_PVS_NUM_FPUS_SHIFT); else - r300->hw.vap_cntl.cmd[1] = 0x0030045A; //0x0030065a /* Dangerous */ + r300->hw.vap_cntl.cmd[1] |= (4 << R300_PVS_NUM_FPUS_SHIFT); r300->hw.vte.cmd[1] = R300_VPORT_X_SCALE_ENA | R300_VPORT_X_OFFSET_ENA @@ -2035,20 +2059,27 @@ static void r300ResetHwState(r300ContextPtr r300) r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_0] = 0x66666666; r300->hw.gb_misc.cmd[R300_GB_MISC_MSPOS_1] = 0x06666666; - /* XXX: Other families? */ + /* num pipes needs to be read back from the GB_PIPE_SELECT register + * on r4xx/r5xx/rs4xx/rs6xx + * should move this to the drm + */ r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] = - R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16; + R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16 /*| R300_GB_SUBPIXEL_1_16*/; switch (r300->radeon.radeonScreen->chip_family) { case CHIP_FAMILY_R300: case CHIP_FAMILY_R350: - case CHIP_FAMILY_RV410: r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= R300_GB_TILE_PIPE_COUNT_R300; break; - case CHIP_FAMILY_R420: + case CHIP_FAMILY_RV350: case CHIP_FAMILY_RV515: - case CHIP_FAMILY_R520: case CHIP_FAMILY_RV530: + case CHIP_FAMILY_RV410: + r300->hw.gb_misc.cmd[R300_GB_MISC_TILE_CONFIG] |= + R300_GB_TILE_PIPE_COUNT_RV300; + break; + case CHIP_FAMILY_R420: + case CHIP_FAMILY_R520: case CHIP_FAMILY_R580: case CHIP_FAMILY_RV560: case CHIP_FAMILY_RV570: @@ -2329,28 +2360,6 @@ static void r500SetupPixelShader(r300ContextPtr rmesa) /* emit the standard zero shader */ R300_STATECHANGE(rmesa, r500fp); i = 1; - rmesa->hw.r500fp.cmd[i++] = 0x7808; - rmesa->hw.r500fp.cmd[i++] = R500_TEX_ID(0) | R500_TEX_INST_LD | R500_TEX_SEM_ACQUIRE | R500_TEX_IGNORE_UNCOVERED; - rmesa->hw.r500fp.cmd[i++] = R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | - R500_TEX_SRC_T_SWIZ_G | - R500_TEX_DST_ADDR(0) | - R500_TEX_DST_R_SWIZ_R | - R500_TEX_DST_G_SWIZ_G | - R500_TEX_DST_B_SWIZ_B | - R500_TEX_DST_A_SWIZ_A; - rmesa->hw.r500fp.cmd[i++] = R500_DX_ADDR(0) | - R500_DX_S_SWIZ_R | - R500_DX_T_SWIZ_R | - R500_DX_R_SWIZ_R | - R500_DX_Q_SWIZ_R | - R500_DY_ADDR(0) | - R500_DY_S_SWIZ_R | - R500_DY_T_SWIZ_R | - R500_DY_R_SWIZ_R | - R500_DY_Q_SWIZ_R; - rmesa->hw.r500fp.cmd[i++] = 0x0; - rmesa->hw.r500fp.cmd[i++] = 0x0; - rmesa->hw.r500fp.cmd[i++] = R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | @@ -2388,7 +2397,7 @@ static void r500SetupPixelShader(r300ContextPtr rmesa) R500_ALU_RGBA_B_SWIZ_0 | R500_ALU_RGBA_A_SWIZ_0; - bump_r500fp_count(rmesa->hw.r500fp.cmd, 12); + bump_r500fp_count(rmesa->hw.r500fp.cmd, 6); R300_STATECHANGE(rmesa, r500fp_const); for (i = 0; i < fp->const_nr; i++) { diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 6f9d9124425..2f57d289fe3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -649,7 +649,9 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->chip_flags = RADEON_CHIPSET_TCL; break; - /* RV410 SE chips have half the pipes of regular RV410 */ + /* RV410 SE chips have half the pipes of regular RV410 + * Need to get num pipes form the GB_PIPE_SELECT register + */ case PCI_CHIP_RV410_5E4C: case PCI_CHIP_RV410_5E4F: screen->chip_family = CHIP_FAMILY_RV380; @@ -709,6 +711,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) case PCI_CHIP_R520_710E: case PCI_CHIP_R520_710F: screen->chip_family = CHIP_FAMILY_R520; + //screen->chip_flags = RADEON_CHIPSET_TCL; fprintf(stderr, "Warning, R520 detected, 3D HAHAHAHAHA!!.\n"); break; @@ -751,6 +754,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) case PCI_CHIP_RV515_7210: case PCI_CHIP_RV515_7211: screen->chip_family = CHIP_FAMILY_RV515; + //screen->chip_flags = RADEON_CHIPSET_TCL; fprintf(stderr, "Warning, RV515 detected, 3D HAHAHAHAHA!!.\n"); break; @@ -771,6 +775,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) case PCI_CHIP_RV530_71DA: case PCI_CHIP_RV530_71DE: screen->chip_family = CHIP_FAMILY_RV530; + //screen->chip_flags = RADEON_CHIPSET_TCL; fprintf(stderr, "Warning, RV530 detected, 3D HAHAHAHAHA!!.\n"); break; @@ -790,6 +795,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) case PCI_CHIP_R580_724F: case PCI_CHIP_R580_7284: screen->chip_family = CHIP_FAMILY_R580; + //screen->chip_flags = RADEON_CHIPSET_TCL; fprintf(stderr, "Warning, R580 detected, 3D HAHAHAHAHA!!.\n"); break; @@ -806,6 +812,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) case PCI_CHIP_RV560_7293: case PCI_CHIP_RV560_7297: screen->chip_family = CHIP_FAMILY_RV560; + //screen->chip_flags = RADEON_CHIPSET_TCL; fprintf(stderr, "Warning, RV560 detected, 3D HAHAHAHAHA!!.\n"); break; -- 2.30.2