From 27a1bfbec62c8467cd14a8d44cf4a8a046576b91 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 1 Sep 2014 11:45:47 +0200 Subject: [PATCH] Fixes in old SAT example.ys --- passes/sat/example.ys | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/passes/sat/example.ys b/passes/sat/example.ys index 11f5b924b..cc72faac0 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -1,13 +1,14 @@ read_verilog example.v proc; opt_clean +echo on sat -set y 1'b1 example001 sat -set y 1'b1 example002 sat -set y_sshl 8'hf0 -set y_sshr 8'hf0 -set sh 4'd3 example003 -sat -set y 1'b1 example004 +sat -set y 1'b1 -ignore_unknown_cells example004 sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004 -sat -prove y 1'b0 -show rst,counter,y example004 -sat -prove y 1'b0 -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 +sat -prove y 1'b0 -show rst,counter,y -ignore_unknown_cells example004 +sat -prove y 1'b0 -tempinduct -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 -- 2.30.2