From 27ae41c83dafcec09e870b3cf08b060064dbb122 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 30 Jul 2012 15:23:21 +0000 Subject: [PATCH] radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLowering --- .../drivers/radeon/AMDGPUISelLowering.cpp | 43 +++++- .../drivers/radeon/AMDGPUISelLowering.h | 56 +++++++- .../drivers/radeon/AMDGPUInstrInfo.cpp | 1 + .../drivers/radeon/AMDILISelLowering.cpp | 133 +++++------------- .../drivers/radeon/AMDILISelLowering.h | 127 ----------------- src/gallium/drivers/radeon/AMDILInstrInfo.td | 14 +- .../drivers/radeon/R600ISelLowering.cpp | 4 +- src/gallium/drivers/radeon/R600InstrInfo.cpp | 1 + src/gallium/drivers/radeon/SICodeEmitter.cpp | 1 + src/gallium/drivers/radeon/SIISelLowering.cpp | 4 +- src/gallium/drivers/radeon/SIInstrInfo.cpp | 1 + 11 files changed, 144 insertions(+), 241 deletions(-) delete mode 100644 src/gallium/drivers/radeon/AMDILISelLowering.h diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index 735fe4da50f..31676d86237 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -14,13 +14,19 @@ #include "AMDGPUISelLowering.h" #include "AMDILIntrinsicInfo.h" #include "AMDGPUUtil.h" +#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" using namespace llvm; AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : - AMDILTargetLowering(TM) + TargetLowering(TM, new TargetLoweringObjectFileELF()) { + + // Initialize target lowering borrowed from AMDIL + InitAMDILLowering(); + // We need to custom lower some of the intrinsics setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); @@ -63,7 +69,7 @@ SDValue AMDGPUTargetLowering::LowerReturn( const SmallVectorImpl &OutVals, DebugLoc DL, SelectionDAG &DAG) const { - return DAG.getNode(AMDILISD::RET_FLAG, DL, MVT::Other, Chain); + return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); } //===---------------------------------------------------------------------===// @@ -74,10 +80,23 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { - default: return AMDILTargetLowering::LowerOperation(Op, DAG); + default: + Op.getNode()->dump(); + assert(0 && "Custom lowering code for this" + "instruction is not implemented yet!"); + break; + // AMDIL DAG lowering + case ISD::SDIV: return LowerSDIV(Op, DAG); + case ISD::SREM: return LowerSREM(Op, DAG); + case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); + case ISD::SELECT: return LowerSELECT(Op, DAG); + case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); + case ISD::BRCOND: return LowerBRCOND(Op, DAG); + // AMDGPU DAG lowering case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); } + return Op; } SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, @@ -100,7 +119,7 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, case AMDGPUIntrinsic::AMDIL_fraction: return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); case AMDGPUIntrinsic::AMDIL_mad: - return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1), + return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), Op.getOperand(2), Op.getOperand(3)); case AMDGPUIntrinsic::AMDIL_max: return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), @@ -152,7 +171,7 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, Op.getOperand(1)); SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, Op.getOperand(3)); - return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1), + return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), Op.getOperand(2), OneSubAC); } @@ -304,8 +323,18 @@ void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI, const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { - default: return AMDILTargetLowering::getTargetNodeName(Opcode); - + default: return 0; + // AMDIL DAG nodes + NODE_NAME_CASE(CMOVLOG); + NODE_NAME_CASE(MAD); + NODE_NAME_CASE(CALL); + NODE_NAME_CASE(UMUL); + NODE_NAME_CASE(DIV_INF); + NODE_NAME_CASE(VBUILD); + NODE_NAME_CASE(RET_FLAG); + NODE_NAME_CASE(BRANCH_COND); + + // AMDGPU DAG nodes NODE_NAME_CASE(FRACT) NODE_NAME_CASE(FMAX) NODE_NAME_CASE(SMAX) diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h b/src/gallium/drivers/radeon/AMDGPUISelLowering.h index 3052247f102..c0945cd8dec 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h @@ -15,11 +15,13 @@ #ifndef AMDGPUISELLOWERING_H #define AMDGPUISELLOWERING_H -#include "AMDILISelLowering.h" +#include "llvm/Target/TargetLowering.h" namespace llvm { -class AMDGPUTargetLowering : public AMDILTargetLowering +class MachineRegisterInfo; + +class AMDGPUTargetLowering : public TargetLowering { private: SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; @@ -60,6 +62,44 @@ public: SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; virtual const char* getTargetNodeName(unsigned Opcode) const; +// Functions defined in AMDILISelLowering.cpp +public: + + /// computeMaskedBitsForTargetNode - Determine which of the bits specified + /// in Mask are known to be either zero or one and return them in the + /// KnownZero/KnownOne bitsets. + virtual void computeMaskedBitsForTargetNode(const SDValue Op, + APInt &KnownZero, + APInt &KnownOne, + const SelectionDAG &DAG, + unsigned Depth = 0) const; + + virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, + const CallInst &I, unsigned Intrinsic) const; + + /// isFPImmLegal - We want to mark f32/f64 floating point values as legal. + bool isFPImmLegal(const APFloat &Imm, EVT VT) const; + + /// ShouldShrinkFPConstant - We don't want to shrink f64/f32 constants. + bool ShouldShrinkFPConstant(EVT VT) const; + +private: + void InitAMDILLowering(); + SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; + EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const; + SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; }; namespace AMDGPUISD @@ -67,7 +107,17 @@ namespace AMDGPUISD enum { - AMDGPU_FIRST = AMDILISD::LAST_ISD_NUMBER, + // AMDIL ISD Opcodes + FIRST_NUMBER = ISD::BUILTIN_OP_END, + CMOVLOG, // 32bit FP Conditional move logical instruction + MAD, // 32bit Fused Multiply Add instruction + VBUILD, // scalar to vector mov instruction + CALL, // Function call based on a single integer + UMUL, // 32bit unsigned multiplication + DIV_INF, // Divide with infinity returned on zero divisor + RET_FLAG, + BRANCH_COND, + // End AMDIL ISD Opcodes BITALIGN, FRACT, FMAX, diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp index 16dd3525e92..2af036740ae 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp @@ -18,6 +18,7 @@ #include "AMDIL.h" #include "AMDILUtilityFunctions.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #define GET_INSTRINFO_CTOR diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.cpp b/src/gallium/drivers/radeon/AMDILISelLowering.cpp index f5f756199d9..4f6b0eb9b02 100644 --- a/src/gallium/drivers/radeon/AMDILISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDILISelLowering.cpp @@ -7,12 +7,11 @@ // //==-----------------------------------------------------------------------===// // -// This file implements the interfaces that AMDIL uses to lower LLVM code into a -// selection DAG. +// This file contains TargetLowering functions borrowed from AMDLI. // //===----------------------------------------------------------------------===// -#include "AMDILISelLowering.h" +#include "AMDGPUISelLowering.h" #include "AMDGPURegisterInfo.h" #include "AMDILDevices.h" #include "AMDILIntrinsicInfo.h" @@ -33,8 +32,6 @@ #include "llvm/Target/TargetOptions.h" using namespace llvm; -#define ISDBITCAST ISD::BITCAST -#define MVTGLUE MVT::Glue //===----------------------------------------------------------------------===// // Calling Convention Implementation //===----------------------------------------------------------------------===// @@ -43,6 +40,8 @@ using namespace llvm; //===----------------------------------------------------------------------===// // TargetLowering Implementation Help Functions Begin //===----------------------------------------------------------------------===// +namespace llvm { +namespace AMDGPU { static SDValue getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) { @@ -61,7 +60,7 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) Src = DAG.getSExtOrTrunc(Src, DL, dvt); } } else if (svt.isInteger()) { - unsigned opcode = (asType) ? ISDBITCAST : ISD::SINT_TO_FP; + unsigned opcode = (asType) ? ISD::BITCAST : ISD::SINT_TO_FP; if (!svt.bitsEq(dvt)) { if (dvt.getSimpleVT().SimpleTy == MVT::f32) { Src = DAG.getSExtOrTrunc(Src, DL, MVT::i32); @@ -73,7 +72,7 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) } Src = DAG.getNode(opcode, DL, dvt, Src); } else if (dvt.isInteger()) { - unsigned opcode = (asType) ? ISDBITCAST : ISD::FP_TO_SINT; + unsigned opcode = (asType) ? ISD::BITCAST : ISD::FP_TO_SINT; if (svt.getSimpleVT().SimpleTy == MVT::f32) { Src = DAG.getNode(opcode, DL, MVT::i32, Src); } else if (svt.getSimpleVT().SimpleTy == MVT::f64) { @@ -86,6 +85,9 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) return Src; } +} // End namespace AMDPGU +} // End namespace llvm + //===----------------------------------------------------------------------===// // TargetLowering Implementation Help Functions End //===----------------------------------------------------------------------===// @@ -93,8 +95,7 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) //===----------------------------------------------------------------------===// // TargetLowering Class Implementation Begins //===----------------------------------------------------------------------===// - AMDILTargetLowering::AMDILTargetLowering(TargetMachine &TM) -: TargetLowering(TM, new TargetLoweringObjectFileELF()) +void AMDGPUTargetLowering::InitAMDILLowering() { int types[] = { @@ -167,9 +168,6 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) setOperationAction(ISD::BRIND, VT, Expand); // TODO: Implement custom UREM/SREM routines setOperationAction(ISD::SREM, VT, Expand); - setOperationAction(ISD::GlobalAddress, VT, Custom); - setOperationAction(ISD::JumpTable, VT, Custom); - setOperationAction(ISD::ConstantPool, VT, Custom); setOperationAction(ISD::SELECT, VT, Custom); setOperationAction(ISD::SMUL_LOHI, VT, Expand); setOperationAction(ISD::UMUL_LOHI, VT, Expand); @@ -273,6 +271,7 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand); setOperationAction(ISD::BUILD_VECTOR, MVT::Other, Custom); + // Use the default implementation. setOperationAction(ISD::ConstantFP , MVT::f32 , Legal); setOperationAction(ISD::Constant , MVT::i32 , Legal); @@ -293,32 +292,15 @@ getConversionNode(SelectionDAG &DAG, SDValue& Src, SDValue& Dst, bool asType) #undef numFloatTypes } -const char * -AMDILTargetLowering::getTargetNodeName(unsigned Opcode) const -{ - switch (Opcode) { - default: return 0; - case AMDILISD::CMOVLOG: return "AMDILISD::CMOVLOG"; - case AMDILISD::MAD: return "AMDILISD::MAD"; - case AMDILISD::CALL: return "AMDILISD::CALL"; - case AMDILISD::SELECT_CC: return "AMDILISD::SELECT_CC"; - case AMDILISD::UMUL: return "AMDILISD::UMUL"; - case AMDILISD::DIV_INF: return "AMDILISD::DIV_INF"; - case AMDILISD::VBUILD: return "AMDILISD::VBUILD"; - case AMDILISD::RET_FLAG: return "AMDILISD::RET_FLAG"; - case AMDILISD::BRANCH_COND: return "AMDILISD::BRANCH_COND"; - - }; -} bool -AMDILTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, +AMDGPUTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const { return false; } // The backend supports 32 and 64 bit floating point immediates bool -AMDILTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const +AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { @@ -329,7 +311,7 @@ AMDILTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const } bool -AMDILTargetLowering::ShouldShrinkFPConstant(EVT VT) const +AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { @@ -345,7 +327,7 @@ AMDILTargetLowering::ShouldShrinkFPConstant(EVT VT) const // combiner. void -AMDILTargetLowering::computeMaskedBitsForTargetNode( +AMDGPUTargetLowering::computeMaskedBitsForTargetNode( const SDValue Op, APInt &KnownZero, APInt &KnownOne, @@ -357,7 +339,7 @@ AMDILTargetLowering::computeMaskedBitsForTargetNode( KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything switch (Op.getOpcode()) { default: break; - case AMDILISD::SELECT_CC: + case ISD::SELECT_CC: DAG.ComputeMaskedBits( Op.getOperand(1), KnownZero, @@ -384,47 +366,8 @@ AMDILTargetLowering::computeMaskedBitsForTargetNode( // Other Lowering Hooks //===----------------------------------------------------------------------===// -// Recursively assign SDNodeOrdering to any unordered nodes -// This is necessary to maintain source ordering of instructions -// under -O0 to avoid odd-looking "skipping around" issues. - static const SDValue -Ordered( SelectionDAG &DAG, unsigned order, const SDValue New ) -{ - if (order != 0 && DAG.GetOrdering( New.getNode() ) == 0) { - DAG.AssignOrdering( New.getNode(), order ); - for (unsigned i = 0, e = New.getNumOperands(); i < e; ++i) - Ordered( DAG, order, New.getOperand(i) ); - } - return New; -} - -#define LOWER(A) \ - case ISD:: A: \ -return Ordered( DAG, DAG.GetOrdering( Op.getNode() ), Lower##A(Op, DAG) ) - -SDValue -AMDILTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const -{ - switch (Op.getOpcode()) { - default: - Op.getNode()->dump(); - assert(0 && "Custom lowering code for this" - "instruction is not implemented yet!"); - break; - LOWER(SDIV); - LOWER(SREM); - LOWER(BUILD_VECTOR); - LOWER(SELECT); - LOWER(SIGN_EXTEND_INREG); - LOWER(BRCOND); - } - return Op; -} - -#undef LOWER - SDValue -AMDILTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const { EVT OVT = Op.getValueType(); SDValue DST; @@ -442,7 +385,7 @@ AMDILTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const } SDValue -AMDILTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const { EVT OVT = Op.getValueType(); SDValue DST; @@ -461,7 +404,7 @@ AMDILTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const } SDValue -AMDILTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const +AMDGPUTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const { EVT VT = Op.getValueType(); SDValue Nodes1; @@ -469,7 +412,7 @@ AMDILTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const SDValue third; SDValue fourth; DebugLoc DL = Op.getDebugLoc(); - Nodes1 = DAG.getNode(AMDILISD::VBUILD, + Nodes1 = DAG.getNode(AMDGPUISD::VBUILD, DL, VT, Op.getOperand(0)); #if 0 @@ -527,21 +470,21 @@ AMDILTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const } SDValue -AMDILTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { SDValue Cond = Op.getOperand(0); SDValue LHS = Op.getOperand(1); SDValue RHS = Op.getOperand(2); DebugLoc DL = Op.getDebugLoc(); - Cond = getConversionNode(DAG, Cond, Op, true); - Cond = DAG.getNode(AMDILISD::CMOVLOG, + Cond = AMDGPU::getConversionNode(DAG, Cond, Op, true); + Cond = DAG.getNode(AMDGPUISD::CMOVLOG, DL, Op.getValueType(), Cond, LHS, RHS); return Cond; } SDValue -AMDILTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const { SDValue Data = Op.getOperand(0); VTSDNode *BaseType = cast(Op.getOperand(1)); @@ -572,7 +515,7 @@ AMDILTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const return Data; } EVT -AMDILTargetLowering::genIntType(uint32_t size, uint32_t numEle) const +AMDGPUTargetLowering::genIntType(uint32_t size, uint32_t numEle) const { int iSize = (size * numEle); int vEle = (iSize >> ((size == 64) ? 6 : 5)); @@ -595,14 +538,14 @@ AMDILTargetLowering::genIntType(uint32_t size, uint32_t numEle) const } SDValue -AMDILTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { SDValue Chain = Op.getOperand(0); SDValue Cond = Op.getOperand(1); SDValue Jump = Op.getOperand(2); SDValue Result; Result = DAG.getNode( - AMDILISD::BRANCH_COND, + AMDGPUISD::BRANCH_COND, Op.getDebugLoc(), Op.getValueType(), Chain, Jump, Cond); @@ -610,7 +553,7 @@ AMDILTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const } SDValue -AMDILTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const { DebugLoc DL = Op.getDebugLoc(); EVT OVT = Op.getValueType(); @@ -654,7 +597,7 @@ AMDILTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib); // float fq = native_divide(fa, fb); - SDValue fq = DAG.getNode(AMDILISD::DIV_INF, DL, FLTTY, fa, fb); + SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb); // fq = trunc(fq); fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq); @@ -663,7 +606,7 @@ AMDILTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq); // float fr = mad(fqneg, fb, fa); - SDValue fr = DAG.getNode(AMDILISD::MAD, DL, FLTTY, fqneg, fb, fa); + SDValue fr = DAG.getNode(AMDGPUISD::MAD, DL, FLTTY, fqneg, fb, fa); // int iq = (int)fq; SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq); @@ -682,7 +625,7 @@ AMDILTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE); } // jq = (cv ? jq : 0); - jq = DAG.getNode(AMDILISD::CMOVLOG, DL, OVT, cv, jq, + jq = DAG.getNode(AMDGPUISD::CMOVLOG, DL, OVT, cv, jq, DAG.getConstant(0, OVT)); // dst = iq + jq; iq = DAG.getSExtOrTrunc(iq, DL, OVT); @@ -691,7 +634,7 @@ AMDILTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const } SDValue -AMDILTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const { DebugLoc DL = Op.getDebugLoc(); EVT OVT = Op.getValueType(); @@ -758,13 +701,13 @@ AMDILTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const } SDValue -AMDILTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const { return SDValue(Op.getNode(), 0); } SDValue -AMDILTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const { DebugLoc DL = Op.getDebugLoc(); EVT OVT = Op.getValueType(); @@ -782,7 +725,7 @@ AMDILTargetLowering::LowerSREM8(SDValue Op, SelectionDAG &DAG) const } SDValue -AMDILTargetLowering::LowerSREM16(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSREM16(SDValue Op, SelectionDAG &DAG) const { DebugLoc DL = Op.getDebugLoc(); EVT OVT = Op.getValueType(); @@ -800,7 +743,7 @@ AMDILTargetLowering::LowerSREM16(SDValue Op, SelectionDAG &DAG) const } SDValue -AMDILTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const { DebugLoc DL = Op.getDebugLoc(); EVT OVT = Op.getValueType(); @@ -849,7 +792,7 @@ AMDILTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1); // umul r20, r20, r1 - r20 = DAG.getNode(AMDILISD::UMUL, DL, OVT, r20, r1); + r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1); // sub r0, r0, r20 r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20); @@ -863,7 +806,7 @@ AMDILTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const } SDValue -AMDILTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const +AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const { return SDValue(Op.getNode(), 0); } diff --git a/src/gallium/drivers/radeon/AMDILISelLowering.h b/src/gallium/drivers/radeon/AMDILISelLowering.h deleted file mode 100644 index e660492656f..00000000000 --- a/src/gallium/drivers/radeon/AMDILISelLowering.h +++ /dev/null @@ -1,127 +0,0 @@ -//===-- AMDILISelLowering.h - AMDIL DAG Lowering Interface ------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// -// -// This file defines the interfaces that AMDIL uses to lower LLVM code into a -// selection DAG. -// -//===----------------------------------------------------------------------===// - -#ifndef AMDIL_ISELLOWERING_H_ -#define AMDIL_ISELLOWERING_H_ -#include "AMDIL.h" -#include "llvm/CodeGen/CallingConvLower.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Target/TargetLowering.h" - -namespace llvm -{ - namespace AMDILISD - { - enum - { - FIRST_NUMBER = ISD::BUILTIN_OP_END, - CMOVLOG, // 32bit FP Conditional move logical instruction - MAD, // 32bit Fused Multiply Add instruction - VBUILD, // scalar to vector mov instruction - CALL, // Function call based on a single integer - SELECT_CC, // Select the correct conditional instruction - UMUL, // 32bit unsigned multiplication - DIV_INF, // Divide with infinity returned on zero divisor - RET_FLAG, - BRANCH_COND, - LAST_ISD_NUMBER - }; - } // AMDILISD - - class MachineBasicBlock; - class MachineInstr; - class DebugLoc; - class TargetInstrInfo; - - class AMDILTargetLowering : public TargetLowering - { - public: - AMDILTargetLowering(TargetMachine &TM); - - virtual SDValue - LowerOperation(SDValue Op, SelectionDAG &DAG) const; - - /// computeMaskedBitsForTargetNode - Determine which of - /// the bits specified - /// in Mask are known to be either zero or one and return them in - /// the - /// KnownZero/KnownOne bitsets. - virtual void - computeMaskedBitsForTargetNode( - const SDValue Op, - APInt &KnownZero, - APInt &KnownOne, - const SelectionDAG &DAG, - unsigned Depth = 0 - ) const; - - virtual bool - getTgtMemIntrinsic(IntrinsicInfo &Info, - const CallInst &I, unsigned Intrinsic) const; - virtual const char* - getTargetNodeName( - unsigned Opcode - ) const; - // We want to mark f32/f64 floating point values as - // legal - bool - isFPImmLegal(const APFloat &Imm, EVT VT) const; - // We don't want to shrink f64/f32 constants because - // they both take up the same amount of space and - // we don't want to use a f2d instruction. - bool ShouldShrinkFPConstant(EVT VT) const; - - SDValue - LowerSREM(SDValue Op, SelectionDAG &DAG) const; - SDValue - LowerSREM8(SDValue Op, SelectionDAG &DAG) const; - SDValue - LowerSREM16(SDValue Op, SelectionDAG &DAG) const; - SDValue - LowerSREM32(SDValue Op, SelectionDAG &DAG) const; - SDValue - LowerSREM64(SDValue Op, SelectionDAG &DAG) const; - - SDValue - LowerSDIV(SDValue Op, SelectionDAG &DAG) const; - SDValue - LowerSDIV24(SDValue Op, SelectionDAG &DAG) const; - SDValue - LowerSDIV32(SDValue Op, SelectionDAG &DAG) const; - SDValue - LowerSDIV64(SDValue Op, SelectionDAG &DAG) const; - - SDValue - LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; - - SDValue - LowerSELECT(SDValue Op, SelectionDAG &DAG) const; - - SDValue - LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; - - EVT - genIntType(uint32_t size = 32, uint32_t numEle = 1) const; - - SDValue - LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; - - SDValue - LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; - - }; // AMDILTargetLowering -} // end namespace llvm - -#endif // AMDIL_ISELLOWERING_H_ diff --git a/src/gallium/drivers/radeon/AMDILInstrInfo.td b/src/gallium/drivers/radeon/AMDILInstrInfo.td index e9e87b7c2ac..677a7236d5f 100644 --- a/src/gallium/drivers/radeon/AMDILInstrInfo.td +++ b/src/gallium/drivers/radeon/AMDILInstrInfo.td @@ -103,32 +103,32 @@ def SDTIL_BRCond : SDTypeProfile<0, 2, [ //===----------------------------------------------------------------------===// // Flow Control DAG Nodes //===----------------------------------------------------------------------===// -def IL_brcond : SDNode<"AMDILISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; +def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; //===----------------------------------------------------------------------===// // Call/Return DAG Nodes //===----------------------------------------------------------------------===// -def IL_retflag : SDNode<"AMDILISD::RET_FLAG", SDTNone, +def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; //===--------------------------------------------------------------------===// // Instructions //===--------------------------------------------------------------------===// // Floating point math functions -def IL_cmov_logical : SDNode<"AMDILISD::CMOVLOG", SDTIL_GenTernaryOp>; -def IL_div_inf : SDNode<"AMDILISD::DIV_INF", SDTIL_GenBinaryOp>; -def IL_mad : SDNode<"AMDILISD::MAD", SDTIL_GenTernaryOp>; +def IL_cmov_logical : SDNode<"AMDGPUISD::CMOVLOG", SDTIL_GenTernaryOp>; +def IL_div_inf : SDNode<"AMDGPUISD::DIV_INF", SDTIL_GenBinaryOp>; +def IL_mad : SDNode<"AMDGPUISD::MAD", SDTIL_GenTernaryOp>; //===----------------------------------------------------------------------===// // Integer functions //===----------------------------------------------------------------------===// -def IL_umul : SDNode<"AMDILISD::UMUL" , SDTIntBinOp, +def IL_umul : SDNode<"AMDGPUISD::UMUL" , SDTIntBinOp, [SDNPCommutative, SDNPAssociative]>; //===----------------------------------------------------------------------===// // Vector functions //===----------------------------------------------------------------------===// -def IL_vbuild : SDNode<"AMDILISD::VBUILD", SDTIL_GenVecBuild, +def IL_vbuild : SDNode<"AMDGPUISD::VBUILD", SDTIL_GenVecBuild, []>; //===--------------------------------------------------------------------===// diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index 844e071a066..768c7db3140 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -16,7 +16,9 @@ #include "AMDGPUUtil.h" #include "R600InstrInfo.h" #include "R600MachineFunctionInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SelectionDAG.h" using namespace llvm; @@ -300,7 +302,7 @@ SDValue R600TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const DAG.getConstant(0, MVT::i32), CC); Result = DAG.getNode( - AMDILISD::BRANCH_COND, + AMDGPUISD::BRANCH_COND, CmpValue.getDebugLoc(), MVT::Other, Chain, JumpT, CmpValue); diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp index 77679abbfc1..74fab60d18b 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.cpp +++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp @@ -15,6 +15,7 @@ #include "AMDGPUTargetMachine.h" #include "AMDILSubtarget.h" #include "R600RegisterInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #define GET_INSTRINFO_CTOR #include "AMDGPUGenDFAPacketizer.inc" diff --git a/src/gallium/drivers/radeon/SICodeEmitter.cpp b/src/gallium/drivers/radeon/SICodeEmitter.cpp index 573e6fae007..fc9f0458bfe 100644 --- a/src/gallium/drivers/radeon/SICodeEmitter.cpp +++ b/src/gallium/drivers/radeon/SICodeEmitter.cpp @@ -20,6 +20,7 @@ #include "SIMachineFunctionInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetMachine.h" diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp index 591968a079d..a14cb6f4106 100644 --- a/src/gallium/drivers/radeon/SIISelLowering.cpp +++ b/src/gallium/drivers/radeon/SIISelLowering.cpp @@ -15,7 +15,9 @@ #include "SIISelLowering.h" #include "SIInstrInfo.h" #include "SIRegisterInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SelectionDAG.h" using namespace llvm; @@ -267,7 +269,7 @@ SDValue SITargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const CC); Result = DAG.getNode( - AMDILISD::BRANCH_COND, + AMDGPUISD::BRANCH_COND, CmpValue.getDebugLoc(), MVT::Other, Chain, JumpT, CmpValue); diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp b/src/gallium/drivers/radeon/SIInstrInfo.cpp index 26f45fce417..f3e69a0ea9d 100644 --- a/src/gallium/drivers/radeon/SIInstrInfo.cpp +++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp @@ -14,6 +14,7 @@ #include "SIInstrInfo.h" #include "AMDGPUTargetMachine.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/MC/MCInstrDesc.h" -- 2.30.2