From 27b0f1b39b99935580be5abbc766e241746a0578 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 15:38:07 +0100 Subject: [PATCH] correct link --- simple_v_extension/abridged_spec.mdwn | 2 +- simple_v_extension/vblock_format.mdwn | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index 8bf2ff7d9..9cf284f44 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -261,7 +261,7 @@ of the RISC-V Spec. It permits an optional VL/MVL/SUBVL block, up to 4 and the rest of the instruction may be either standard RV opcodes or the SVPrefix opcodes ([[sv_prefix_proposal]]) -[[!inline raw="yes" pages="simple_v_extension/vblock_table_format" ]] +[[!inline raw="yes" pages="simple_v_extension/vblock_format_table" ]] For full details see ancillary resource: [[vblock_format]] diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn index bf39c4d2c..d442ceaa7 100644 --- a/simple_v_extension/vblock_format.mdwn +++ b/simple_v_extension/vblock_format.mdwn @@ -23,7 +23,7 @@ The format is: Thus, the variable-length format from Section 1.5 of the RISC-V ISA is used as follows: -[[!inline raw="yes" pages="simple_v_extension/vblock_table_format" ]] +[[!inline raw="yes" pages="simple_v_extension/vblock_format_table" ]] Note: this format is very similar to that used in [[sv_prefix_proposal]] -- 2.30.2