From 27b5e32e94cf79c065a49d184b5a0dcad83399c3 Mon Sep 17 00:00:00 2001 From: Ian Jiang Date: Fri, 15 Nov 2019 10:07:06 +0800 Subject: [PATCH] arch-riscv: Fix disassembling of immediate for U-type instructions For U-type instructions auipc and lui, the 20-bit immediate is left-shifted by 12 bits in decoding. While the original Gem5 gives the left-shifted value directly in disassembly. This patch fixes the problem by - Assign the original 20-bit immediate to internal variable "imm". - Output "imm" directly in disassembly, as how the original Gem5 does. - Do the left-shift to "imm" later in the function defining of each instruction, rather than in decoding. Change-Id: I300e26fd9c79478783c39fcd6ff70ea06db88884 Signed-off-by: Ian Jiang Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22564 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Alec Roelke Maintainer: Jason Lowe-Power --- src/arch/riscv/isa/decoder.isa | 4 ++-- src/arch/riscv/isa/formats/standard.isa | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 8fcfba6ca..78cb78ce6 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -443,7 +443,7 @@ decode QUADRANT default Unknown::unknown() { } 0x05: UOp::auipc({{ - Rd = PC + imm; + Rd = PC + (sext<20>(imm) << 12); }}); 0x06: decode FUNCT3 { @@ -787,7 +787,7 @@ decode QUADRANT default Unknown::unknown() { } 0x0d: UOp::lui({{ - Rd = (uint64_t)imm; + Rd = (uint64_t)(sext<20>(imm) << 12); }}); 0x0e: decode FUNCT3 { diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index 15d268112..3c71fc8fb 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -341,7 +341,7 @@ def format Jump(code, *opt_flags) {{ def format UOp(code, *opt_flags) {{ regs = ['_destRegIdx[0]'] iop = InstObjParams(name, Name, 'ImmOp', - {'code': code, 'imm_code': 'imm = sext<20>(IMM20) << 12;', + {'code': code, 'imm_code': 'imm = IMM20;', 'regs': ','.join(regs)}, opt_flags) header_output = ImmDeclare.subst(iop) decoder_output = ImmConstructor.subst(iop) -- 2.30.2