From 2809ae3d445bc10a79f119946439431ba73bb069 Mon Sep 17 00:00:00 2001
From: Tom Stellard <thomas.stellard@amd.com>
Date: Wed, 29 Aug 2012 11:39:38 -0400
Subject: [PATCH] radeon/llvm: Fix encoding of FP immediates on SI

---
 .../drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp        | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
index bc0b968bee0..5569cf6c3cc 100644
--- a/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/src/gallium/drivers/radeon/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -239,9 +239,14 @@ uint64_t SIMCCodeEmitter::VOPPostEncode(const MCInst &MI, uint64_t Value) const{
         Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
       }
     } else if (MO.isFPImm()) {
+      union {
+        float f;
+        uint32_t i;
+      } Imm;
       // XXX: Not all instructions can use inline literals
       // XXX: We should make sure this is a 32-bit constant
-      Value |= ((uint64_t)MO.getFPImm()) << 32;
+      Imm.f = MO.getFPImm();
+      Value |= ((uint64_t)Imm.i) << 32;
     }
   }
   return Value;
-- 
2.30.2