From 2814d7626846b954214132fd4a9b63e5c9b0e9d7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Apr 2019 10:20:02 +0100 Subject: [PATCH] generate il file before running simulation, test 7 --- src/add/test_buf_pipe.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index f88d3005..ee1734e8 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -1063,8 +1063,6 @@ if __name__ == '__main__': dut = ExampleAddRecordPipe() data=data_dict() test = Test5(dut, resultfn_7, data=data) - run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd") - ports = [dut.p.i_valid, dut.n.i_ready, dut.n.o_valid, dut.p.o_ready, dut.p.i_data.src1, dut.p.i_data.src2, @@ -1072,6 +1070,7 @@ if __name__ == '__main__': vl = rtlil.convert(dut, ports=ports) with open("test_recordcomb_pipe.il", "w") as f: f.write(vl) + run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd") print ("test 8") dut = ExampleBufPipeAddClass() -- 2.30.2